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IBM0418A41DLAB-3 PDF预览

IBM0418A41DLAB-3

更新时间: 2024-01-21 08:03:31
品牌 Logo 应用领域
国际商业机器公司 - IBM 静态存储器内存集成电路
页数 文件大小 规格书
25页 218K
描述
Standard SRAM, 256KX18, 1.7ns, CMOS, PBGA119, BGA-119

IBM0418A41DLAB-3 技术参数

生命周期:Contact Manufacturer零件包装代码:BGA
包装说明:BGA, BGA119,7X17,50针数:119
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.73
Is Samacsys:NBase Number Matches:1

IBM0418A41DLAB-3 数据手册

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IBM0418A81DLAB  
IBM0418A41DLAB  
IBM0436A81DLAB  
IBM0436A41DLAB  
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM  
Features  
• 8Mb: 256K x 36 or 512K x 18 organizations  
4Mb: 128K x 36 or 256K x 18 organizations  
• Registered Outputs  
• Common I/O  
• 0.25 Micron CMOS technology  
• Asynchronous Output Enable  
• Synchronous Power Down Input  
• Synchronous Pipeline Mode of Operation with  
Self-Timed Late Write  
• Boundary Scan using limited set of JTAG  
1149.1 functions  
• Single Differential HSTL Clock  
• +3.3V Power Supply, Ground, 2.1V V  
, and  
DDQ  
• Byte Write Capability and Global Write Enable  
1.0V V  
REF  
• 7 x 17 Bump Ball Grid Array Package with  
SRAM JEDEC Standard Pinout and Boundary  
SCAN Order  
• HSTL Input and Output levels  
• Registered Addresses, Write Enables, Synchro-  
nous Select, and Data Ins  
Description  
The 4Mb and 8Mb SRAMs—IBM0436A41DLAB,  
IBM0418A41DLAB, IBM0418A81DLAB, and  
IBM0436A81DLAB—are Synchronous Pipeline  
Mode, high-performance CMOS Static Random  
Access Memories that are versatile, wide I/O, and  
can achieve 3ns cycle times. Dual differential K  
clocks are used to initiate the read/write operation  
and all internal operations are self-timed. At the ris-  
ing edge of the K clock, all Addresses, Write-  
Enables, Sync Select, and Data Ins are registered  
internally. Data Outs are updated from output regis-  
ters off the next rising edge of the K clock. An inter-  
nal Write buffer allows write data to follow one cycle  
after addresses and controls. The chip is operated  
with a single +3.3V power supply and is compatible  
with HSTL I/O interfaces.  
crrh3319.08  
02/01  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
Page 1 of 25  

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