Datasheet > IBM0312404CT3B-75D

IBM0312404CT3B-75D

更新时间： 2024-01-01 00:10:45

品牌	Logo	应用领域
国际商业机器公司 - IBM		动态存储器光电二极管内存集成电路
页数	文件大小	规格书
69页	1067K
描述
Synchronous DRAM, 32MX4, 5.4ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54

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IBM0312404CT3B-75D 技术参数

生命周期：	Obsolete	零件包装代码：	TSOP2
包装说明：	TSOP2,	针数：	54
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.02	风险等级：	5.27
访问模式：	FOUR BANK PAGE BURST	最长访问时间：	5.4 ns
其他特性：	AUTO/SELF REFRESH	JESD-30 代码：	R-PDSO-G54
长度：	22.22 mm	内存密度：	134217728 bit
内存集成电路类型：	SYNCHRONOUS DRAM	内存宽度：	4
功能数量：	1	端口数量：	1
端子数量：	54	字数：	33554432 words
字数代码：	32000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	32MX4	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP2	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE	认证状态：	Not Qualified
座面最大高度：	1.2 mm	自我刷新：	YES
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	DUAL	宽度：	10.16 mm
Base Number Matches：	1

IBM0312404CT3B-75D 数据手册

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IBM0312164 IBM0312804

IBM0312404 IBM03124B4

Advance 0.1

Features

128Mb Synchronous DRAM - Die Revision B

• Programmable CAS Latency: 2, 3

• High Performance:

• Programmable Burst Length: 1, 2, 4, 8

-75H -75D -75A, -260, -360, -10,

CL=2 CL=3 CL=3 CL=2 CL=3 CL=3

Units

• Programmable Wrap: Sequential or Interleave

Clock

Frequency

133 133 133 100 100 100 MHz

• Multiple Burst Read with Single Write Option

• Automatic and Controlled Precharge Command

• Data Mask for Read/Write control (x4, x8)

• Dual Data Mask for byte control (x16)

• Auto Refresh (CBR) and Self Refresh

• Suspend Mode and Power Down Mode

• Standard Power operation

Clock Cycle

7.5

—

7.5

—

7.5

—

Clock Access

Time

Clock Access

5.4

Time

1. Terminated load. See AC Characteristics on page 39.

2. Unterminated load. See AC Characteristics on page 39.

3. t = t

= 2 CKs

RCD

• 4096 refresh cycles/64ms

• Random Column Address every CK (1-N Rule)

• Single 3.3V ± 0.3V Power Supply

• LVTTL compatible

• Single Pulsed RAS Interface

• Fully Synchronous to Positive Clock Edge

• Four Banks controlled by BS0/BS1

(Bank Select)

• Package: 54-pin 400 mil TSOP-Type II

2 High Stack TSOJ

Description

The IBM0312404, IBM0312804, and IBM0312164

are four-bank Synchronous DRAMs organized as

8Mbit x 4 I/O x 4 Bank, 4Mbit x 8 I/O x 4 Bank, and

2Mbit x 16 I/O x 4 Bank, respectively. IBM03124B4,

a stacked version of the x4 component, is also

offered. These synchronous devices achieve high-

speed data transfer rates of up to 133MHz by

employing a pipeline chip architecture that synchro-

nizes the output data to a system clock. The chip is

fabricated with IBM’s advanced 128Mbit single tran-

sistor CMOS DRAM process technology.

and two bank select addresses (BS0, BS1) are

strobed with RAS. Eleven column addresses (A0-

A9, A11) plus bank select addresses and A10 are

strobed with CAS. Column address A11 is dropped

on the x8 device, and column addresses A11 and

A9 are dropped on the x16 device. Access to the

lower or upper DRAM in a stacked device is con-

trolled by CS0 and CS1, respectively.

Prior to any access operation, the CAS latency,

burst length, and burst sequence must be pro-

grammed into the device by address inputs A0-A11,

BS0, BS1 during a mode register set cycle. In addi-

tion, it is possible to program a multiple burst

sequence with single write cycle for write through

cache operation.

The device is designed to comply with all JEDEC

standards set for synchronous DRAM products,

both electrically and mechanically. All of the control,

address, and data input/output (I/O or DQ) circuits

are synchronized with the positive edge of an exter-

nally supplied clock.

Operating the four memory banks in an interleave

fashion allows random access operation to occur at

a higher rate than is possible with standard DRAMs.

A sequential and gapless data rate of up to 133MHz

is possible depending on burst length, CAS latency,

and speed grade of the device. Simultaneous opera-

tion of both decks of a stacked device is allowed,

depending on the operation being done. Auto

Refresh (CBR) and Self Refresh operation are sup-

ported.

RAS, CAS, WE, and CS are pulsed signals which

are examined at the positive edge of each externally

applied clock (CK). Internal chip operating modes

are defined by combinations of these signals and a

command decoder initiates the necessary timings

for each operation. A fourteen bit address bus

accepts address data in the conventional RAS/CAS

multiplexing style. Twelve row addresses (A0-A11)

Use is further subject to the provisions at the end of this document.

06K7582.H03335

05/00

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与IBM0312404CT3B-75D相关器件

型号	品牌	描述	获取价格	数据表
IBM0312404CT3B-75H	IBM	Synchronous DRAM, 32MX4, 5.4ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54	获取价格
IBM0312804CT3B-75H	IBM	Synchronous DRAM, 16MX8, 5.4ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54	获取价格
IBM0316169CT3-10H	ETC	x16 SDRAM	获取价格
IBM0316169CT3-11	IBM	Synchronous DRAM, 1MX16, 10ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50	获取价格
IBM0316169CT3-12H	ETC	x16 SDRAM	获取价格
IBM0316169CT3-13	IBM	Synchronous DRAM, 1MX16, 12ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50	获取价格

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