Datasheet > HYMD564M646L8-K

HYMD564M646L8-K

更新时间： 2024-11-11 20:05:23

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器双倍数据速率内存集成电路
页数	文件大小	规格书
16页	236K
描述
DDR DRAM Module, 64MX64, 0.75ns, CMOS, 67.60 X 31.75 X 1 MM, SODIMM-200

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HYMD564M646L8-K 技术参数

生命周期：	Obsolete	零件包装代码：	MODULE
包装说明：	DIMM,	针数：	200
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.36	风险等级：	5.84
访问模式：	SINGLE BANK PAGE BURST	最长访问时间：	0.75 ns
其他特性：	AUTO/SELF REFRESH	JESD-30 代码：	R-XDMA-N200
内存密度：	4294967296 bit	内存集成电路类型：	DDR DRAM MODULE
内存宽度：	64	功能数量：	1
端口数量：	1	端子数量：	200
字数：	67108864 words	字数代码：	64000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	64MX64
封装主体材料：	UNSPECIFIED	封装代码：	DIMM
封装形状：	RECTANGULAR	封装形式：	MICROELECTRONIC ASSEMBLY
认证状态：	Not Qualified	自我刷新：	YES
最大供电电压 (Vsup)：	2.7 V	最小供电电压 (Vsup)：	2.3 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	NO
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	NO LEAD	端子位置：	DUAL
Base Number Matches：	1

HYMD564M646L8-K 数据手册

64Mx64 bits

Unbuffered DDR SO-DIMM

HYMD564M646(L)8-K/H/L

DESCRIPTION

Preliminary

Hynix HYMD564M646(L)8-K/H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small Outline

Dual In-Line Memory Modules (SO-DIMMs) which are organized as 64Mx64 high-speed memory arrays. Hynix

HYMD564M646(L)8-K/H/L series consists of eight 64Mx8 DDR SDRAM in 400mil TSOP II packages on a 200pin

glass-epoxy substrate. Hynix HYMD564M646(L)8-K/H/L series provide a high performance 8-byte interface in

67.60mmX 31.75mm form factor of industry standard. It is suitable for easy interchange and addition.

Hynix HYMD564M646(L)8-K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous

operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control

inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on

both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high

bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable

latencies and burst lengths allow variety of device operation in high performance memory system.

Hynix HYMD564M646(L)8-K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is

implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify

DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

FEATURES

•

512MB (64M x 64) Unbuffered DDR SO-DIMM

based on 64Mx8 DDR SDRAM

•

Data inputs on DQS centers when write (centered

DQ)

•

JEDEC Standard 200-pin small outline dual in-line

memory module (SO-DIMM)

Data strobes synchronized with output data for read

and input data for write

•

2.5V +/- 0.2V VDD and VDDQ Power supply

•

Programmable CAS Latency 1.5 / 2 / 2.5 supported

All inputs and outputs are compatible with SSTL_2

interface

Programmable Burst Length 2 / 4 / 8 with both

sequential and interleave mode

•

Fully differential clock operations (CK & /CK) with

100MHz/125MHz/133MHz

•

tRAS Lock-out function supported

Internal four bank operations with single pulsed RAS

Auto refresh and self refresh supported

8192 refresh cycles / 64ms

All addresses and control inputs except Data, Data

strobes and Data masks latched on the rising edges

of the clock

•

Data(DQ), Data strobes and Write masks latched on

both rising and falling edges of the clock

ORDERING INFORMATION

Part No.

Power Supply

Clock Frequency

Interface

Form Pactor

HYMD564M646(L)8-K

HYMD564M646(L)8-H

HYMD564M646(L)8-L

133MHz (*DDR266A)

133MHz (*DDR266B)

125MHz (*DDR200)

VDD=2.5V

VDDQ=2.5V

200pin Unbuffered SO-DIMM

67.6mm x 31.75mm x 1mm

SSTL_2

* JEDEC Defined Specifications compliant

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.2/Jul. 02

12 3 4 5 6 7...16

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