Datasheet > HY5W2A6CLF-PF

HY5W2A6CLF-PF

更新时间： 2024-02-21 01:52:04

品牌	Logo	应用领域
海力士 - HYNIX		时钟动态存储器内存集成电路
页数	文件大小	规格书
24页	407K
描述
Synchronous DRAM, 8MX16, 7ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

HY5W2A6CLF-PF 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	FBGA, BGA54,9X9,32	针数：	54
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.02	风险等级：	5.84
访问模式：	FOUR BANK PAGE BURST	最长访问时间：	7 ns
其他特性：	AUTO/SELF REFRESH	最大时钟频率 (fCLK)：	100 MHz
I/O 类型：	COMMON	交错的突发长度：	1,2,4,8
JESD-30 代码：	R-PBGA-B54	JESD-609代码：	e1
长度：	10.5 mm	内存密度：	134217728 bit
内存集成电路类型：	SYNCHRONOUS DRAM	内存宽度：	16
功能数量：	1	端口数量：	1
端子数量：	54	字数：	8388608 words
字数代码：	8000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：	-25 °C
组织：	8MX16	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	FBGA
封装等效代码：	BGA54,9X9,32	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, FINE PITCH	峰值回流温度（摄氏度）：	260
电源：	1.8/2.5,2.5 V	认证状态：	Not Qualified
刷新周期：	4096	自我刷新：	YES
连续突发长度：	1,2,4,8,FP	最大待机电流：	0.0005 A
子类别：	DRAMs	最大压摆率：	0.155 mA
最大供电电压 (Vsup)：	2.7 V	最小供电电压 (Vsup)：	2.3 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	0.8 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	20	宽度：	8.3 mm
Base Number Matches：	1

HY5W2A6CLF-PF 数据手册

HY5W2A6C(L/S)F-F / HY57W2A1620HC(L/S)T -F

HY5W26CF-F / HY57W281620HCT-F

Precharge

The Precharge command is used to close the open row in a particular bank or the open row in all banks. When the precharge

command is issued with address A10, high, then all banks will be precharged, and If A10 is low, the open row in a particular

bank will be precharged. The bank(s) will be available when the minimum tRP time is met after the precharge command is

issued.

Auto Precharge

The Auto Precharge command is issued to close the open row in a particular bank after READ or WRITE operation. If A10

is high when a READ or WRITE command is issued, the READ or WRITE with Auto Precharge is initiated.

Burst Termination

The Burst Termination is used to terminate the burst operation. This function can be accomplished by asserting a Burst Stop

command or a Precharge command during a burst READ or WRITE operation. The Precharge command interrupts a burst

cycle and close the active bank, and the Burst Stop command terminates the existing burst operation leave the bank open.

Data Mask

The Data Mask comamnd is used to mask READ or WRITE data. During a READ operation, When this command is issued,

data ouputs are disabled and become high impedance after two clock delay. During a WRITE operation, When this command

is issued, data inputs can’t be written with no clock delay.

Clock Suspend

The Clock Suspend command is used to suspend the internal clock of DRAM. During normal access mode, CKE is keeping

High. When CKE is low, it freezes the internal clock and extends data Read and Write operations.

Power Down

The Power Down command is used to reduce standby current. Before this command is issued, all banks must be precharged

and tRP must be passed after a precharge command. Once the Power Down command is initiated by keeping CKE low, all

of the input buffer except CKE are gated off.

Auto Refresh

The Auto Refresh command is used during normal operation and is similar to CBR refresh in Coventional DRAMs. This com-

mand must be issued each time a refresh is required. When an Auto Refresh command is issued , the address bits is “Don’t

care”, because the specific address bits is generated by internal refresh address counter.

Self Refresh

The Self Refresh command is used to retain cell data in the Low Power SDRAM. In the Self Refresh mode, the Low Power

SDRAM operates refresh cycle asynchronously. The Self Refresh command is initiated like an Auto Refresh command ex-

cept CKE is disabled(Low). The Low Power SDRAM can accomplish an special Self Refresh operation by the specific

modes(TCSR, PASR) programmed in extended mode registers. The Low Power SDRAM can control the refresh rate by the

temperature value of TCSR (Temperature Compensated Self Refresh) and select the memory array to be refreshed by the

value of PASR(Partial Array Self Refresh). The Low Power SDRAM can reduce the self refresh current(IDD6) by using these

two modes.

Deep Power Down

The Deep Power Down Mode is used to achieve maximum power reduction by cutting the power of the whole memory array

of the devices. For more information, see the special operation for Low Power consumption of this data sheet.

Rev. 1.3 / Dec. 01

1...5 6 789 10 11...24

下载PDF

与HY5W2A6CLF-PF相关器件

型号	品牌	描述	获取价格	数据表
HY5W2A6CLF-S	HYNIX	Synchronous DRAM, 8MX16, 7ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54	获取价格
HY5W2A6CSF-B	HYNIX	Synchronous DRAM, 8MX16, 9ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54	获取价格
HY5W2A6CSF-H	ETC	SDRAM\|4X2MX16\|CMOS\|BGA\|54PIN\|PLASTIC	获取价格
HY5W2A6CSF-HF	HYNIX	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54	获取价格
HY5W2A6CSF-P	HYNIX	Synchronous DRAM, 8MX16, 7ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54	获取价格
HY5W2A6CSF-PF	HYNIX	Synchronous DRAM, 8MX16, 7ns, CMOS, PBGA54, 8.30 X 10.50 MM, 0.80 MM PITCH, FBGA-54	获取价格

与HY5W2A6CLF-PF相关文章

SG3525资料手册详解：SG3525参数分析、引脚说明、应用介绍
2024-05-23

3
AT89C51单片机资料手册详细解析及应用示例
2024-05-23

5
CP2102资料手册解读：CP2102引脚说明、关键参数分析
2024-05-23

3
资料手册解读：UC3842参数和管脚说明
2024-05-22

5

产品中心

服务支持

精选活动

关于我们

帮助中心

HY5W2A6CLF-PF

HY5W2A6CLF-PF 技术参数

HY5W2A6CLF-PF 数据手册

与HY5W2A6CLF-PF相关器件

与HY5W2A6CLF-PF相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

HY5W2A6CLF-PF

HY5W2A6CLF-PF 技术参数

HY5W2A6CLF-PF 数据手册

与HY5W2A6CLF-PF相关器件

与HY5W2A6CLF-PF相关文章

您还可以找

您在本页遇到什么问题？