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HY57Y281620HCT-P PDF预览

HY57Y281620HCT-P

更新时间: 2024-11-24 20:04:11
品牌 Logo 应用领域
海力士 - HYNIX 时钟动态存储器ISM频段光电二极管内存集成电路
页数 文件大小 规格书
13页 174K
描述
Synchronous DRAM, 8MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54

HY57Y281620HCT-P 技术参数

生命周期:Obsolete零件包装代码:TSOP2
包装说明:TSOP2, TSOP54,.46,32针数:54
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.02风险等级:5.84
访问模式:FOUR BANK PAGE BURST最长访问时间:6 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):100 MHz
I/O 类型:COMMON交错的突发长度:1,2,4,8
JESD-30 代码:R-PDSO-G54JESD-609代码:e6
长度:22.22 mm内存密度:134217728 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:54字数:8388608 words
字数代码:8000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP54,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE电源:3 V
认证状态:Not Qualified刷新周期:4096
座面最大高度:1.2 mm自我刷新:YES
连续突发长度:1,2,4,8,FP最大待机电流:0.001 A
子类别:DRAMs最大压摆率:0.2 mA
最大供电电压 (Vsup):3.3 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN BISMUTH端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
宽度:10.16 mmBase Number Matches:1

HY57Y281620HCT-P 数据手册

 浏览型号HY57Y281620HCT-P的Datasheet PDF文件第2页浏览型号HY57Y281620HCT-P的Datasheet PDF文件第3页浏览型号HY57Y281620HCT-P的Datasheet PDF文件第4页浏览型号HY57Y281620HCT-P的Datasheet PDF文件第5页浏览型号HY57Y281620HCT-P的Datasheet PDF文件第6页浏览型号HY57Y281620HCT-P的Datasheet PDF文件第7页 
HY57Y281620HC(L)T  
4 Banks x 2M x 16bits Synchronous DRAM  
DESCRIPTION  
The Hynix HY57Y281620HC(L)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications  
which require large memory density and high bandwidth. HY57Y281620HC(L)T is organized as 4banks of 2,097,152x16  
HY57Y281620HC(L)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are  
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input  
and output voltage levels are compatible with LVTTL.  
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated  
by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of  
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst  
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)  
FEATURES  
Single 3.0±0.3V power supply  
Auto refresh and self refresh  
All device pins are compatible with LVTTL interface  
4096 refresh cycles / 64ms  
JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin  
pitch  
Programmable Burst Length and Burst Type  
- 1, 2, 4, 8 or Full page for Sequential Burst  
- 1, 2, 4 or 8 for Interleave Burst  
All inputs and outputs referenced to positive edge of system  
clock  
Data mask function by UDQM or LDQM  
Internal four banks operation  
Programmable CAS Latency ; 2, 3 Clocks  
ORDERING INFORMATION  
Part No.  
Clock Frequency  
Power  
Organization  
Interface  
Package  
HY57Y281620HCT-H  
HY57Y281620HCT-P  
HY57Y281620HCT-S  
HY57Y281620HCLT-H  
HY57Y281620HCLT-P  
HY57Y281620HCLT-S  
133MHz  
100MHz  
100MHz  
133MHz  
100MHz  
100MHz  
Normal  
4Banks x 2Mbits  
x16  
LVTTL  
400mil 54pin TSOP II  
Low power  
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for  
use of circuits described. No patent licenses are implied.  
Rev. 0.1/Apr. 02  
2

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