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HY57W2A3220T-HC PDF预览

HY57W2A3220T-HC

更新时间: 2024-11-25 07:12:27
品牌 Logo 应用领域
海力士 - HYNIX 动态存储器光电二极管
页数 文件大小 规格书
25页 372K
描述
Synchronous DRAM, 4MX32, 5.4ns, CMOS, PDSO86, 0.400 X 0.875 INCH, 0.50 MM PITCH, TSOP2-86

HY57W2A3220T-HC 数据手册

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HY5W2A2(L/S)F-C / HY57W2A3220(L/S)T-C  
HY5W22F-C / HY57W283220T-C  
4Banks x 1M x 32bits Synchronous DRAM  
DESCRIPTION  
The Hynix Low Power SDRAM is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G  
cellular phones with internet access and multimedia capabilities, mini-notebook, handheld PCs  
The Hynix HY5W2A2F-C series is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for the memory appli-  
cations which require wide data I/O and high bandwidth. HY5W2A2F-C series is organized as 4banks of  
1,048,576x32.  
The Low Power SDRAM provides for programmable options including CAS latency of 1, 2, or 3, READ or WRITE burst  
length of 1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave). And the Low Power SDRAM  
also provides for special programmable options including Partial Array Self Refresh of 1bank, 2banks, or all banks,  
Temperature Compensated Self Refresh of 15, 45, 70, or 85 degrees C. A burst of Read or Write cycles in progress  
can be terminated by a burst terminate command or can be interrupted and replaced by a new burst Read or Write  
command on any cycle(This pipelined design is not restricted by a 2N rule).  
Deep Power Down Mode is a additional operating mode for Low Power SDRAM. This mode can achieve maximum  
power reduction by removing power to the memory array within each SDRAM. By using this feature, the system can  
cut off alomost all DRAM power without adding the cost of a power switch and giving up mother-board power-line lay-  
out flexibility.  
FEATURES  
Standard SDRAM Protocol  
Internal 4bank operation  
Voltage : VDD = 2.5V, VDDQ = 1.8V & 2.5V  
LVTTL compatible I/O Interface  
Low Voltage interface to reduce I/O power  
Low Power Features ( HY5W22FC / HY57W283220T-C series can’t support these features)  
- PASR(Partial Array Self Refresh)  
- TCSR(Temperature Compensated Self Refresh)  
- Deep Power Down Mode  
Packages : 90ball, 0.8mm pitch FBGA / 86pin, TSOP  
-10 ~ 80C Operation  
ORDERING INFORMATION  
Clock Frequency  
Part No.  
Organization  
Interface  
Package  
CAS Latench  
HY57W2A3220(L/S)T-HC  
HY5W2A2(L/S)F-HC  
133MHz  
CL 3  
4Banks x 1Mbits  
x32  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
HY57W2A3220(L/S)T-8C  
HY5W2A2(L/S)F-8C  
125MHz  
CL 3  
4Banks x 1Mbits  
x32  
90balls FBGA  
(HY5xxxxxxF)  
86pin TSOP-II  
(HY5xxxxxxT)  
HY57W2A3220(L/S)T-PC  
HY5W2A2(L/S)F-PC  
100MHz  
CL 2  
4Banks x 1Mbits  
x32  
HY57W2A3220(L/S)T-SC  
HY5W2A2(L/S)F-SC  
100MHz  
CL 3  
4Banks x 1Mbits  
x32  
HY57W2A3220(L/S)T-BC  
HY5W2A2(L/S)F-BC  
66MHz  
CL 2  
4Banks x 1Mbits  
x32  
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume  
any responsibility for use of circuits described. No patent licenses are implied.  
Rev. 0.5/Nov. 02  

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