Datasheet > 存储 > DRAM> HY57V64420HG

HY57V64420HG

更新时间： 2024-11-30 04:58:03

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器
页数	文件大小	规格书
11页	144K
描述
4 Banks x 4M x 4Bit Synchronous DRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

HY57V64420HG 数据手册

HY57V64420HG

4 Banks x 4M x 4Bit Synchronous DRAM

DESCRIPTION

The Hynix HY57V64420HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which

require large memory density and high bandwidth. HY57V64420HG is organized as 4banks of 4,194,304x4.

HY57V644020HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-

nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output

voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by

a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read

or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or

write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3±0.3V power supply

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

4096 refresh cycles / 64ms

JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin

pitch

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

•

All inputs and outputs referenced to positive edge of system

clock

•

Data mask function by DQM

Internal four banks operation

•

Programmable CAS Latency ; 2, 3 Clocks

ORDERING INFORMATION

Part No.

Clock Frequency

Power

Organization

Interface

Package

HY57V64420HGT-5/55/6/7

HY57V64420HGT-K

HY57V64420HGT-H

HY57V64420HGT-P

HY57V64420HGT-S

HY57V64420HGLT-5/55/6/7

HY57V64420HGLT-K

HY57V64420HGLT-H

HY57V64420HGLT-P

HY57V64420HGLT-S

200/183/166/143MHz

133MHz

Normal

100MHz

4Banks x 4Mbits x4

LVTTL

400mil 54pin TSOP II

200/183/166/143MHz

133MHz

Low power

100MHz

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of

circuits described. No patent licenses are implied.

Rev. 0.4/Nov. 01

12 3 4 5 6 7...11

中文翻译

下载PDF

与HY57V64420HG相关器件

型号	品牌	获取价格	描述	数据表
HY57V64420HGLT	ETC	获取价格	16Mx4\|3.3V\|4K\|6\|SDR SDRAM - 64M
HY57V64420HGLT-5	HYNIX	获取价格	Synchronous DRAM, 16MX4, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V64420HGLT-55	HYNIX	获取价格	Synchronous DRAM, 16MX4, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V64420HGLT-6	HYNIX	获取价格	Synchronous DRAM, 16MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V64420HGLT-7	HYNIX	获取价格	Synchronous DRAM, 16MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V64420HGLT-H	HYNIX	获取价格	4 Banks x 4M x 4Bit Synchronous DRAM
HY57V64420HGLT-K	HYNIX	获取价格	4 Banks x 4M x 4Bit Synchronous DRAM
HY57V64420HGLT-P	HYNIX	获取价格	4 Banks x 4M x 4Bit Synchronous DRAM
HY57V64420HGLTP-55	HYNIX	获取价格	DRAM
HY57V64420HGLTP-6	HYNIX	获取价格	Synchronous DRAM, 16MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE

与HY57V64420HG相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

53
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

42
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

70
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

66

产品中心

服务支持

精选活动

关于我们

帮助中心

HY57V64420HG

HY57V64420HG 数据手册

与HY57V64420HG相关器件

与HY57V64420HG相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

HY57V64420HG

HY57V64420HG 数据手册

与HY57V64420HG相关器件

与HY57V64420HG相关文章

您还可以找

您在本页遇到什么问题？