Datasheet > HY57V64420HGLT-55

HY57V64420HGLT-55

更新时间： 2023-02-26 14:51:14

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器光电二极管
页数	文件大小	规格书
11页	145K
描述
Synchronous DRAM, 16MX4, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54

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HY57V64420HG

4 Banks x 4M x 4Bit Synchronous DRAM

DESCRIPTION

The Hynix HY57V64420HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which

require large memory density and high bandwidth. HY57V64420HG is organized as 4banks of 4,194,304x4.

HY57V644020HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-

nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output

voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by

a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read

or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or

write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3±0.3V power supply

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

4096 refresh cycles / 64ms

JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin

pitch

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

•

All inputs and outputs referenced to positive edge of system

clock

•

Data mask function by DQM

Internal four banks operation

•

Programmable CAS Latency ; 2, 3 Clocks

ORDERING INFORMATION

Part No.

Clock Frequency

Power

Organization

Interface

Package

HY57V64420HGT-5/55/6/7

HY57V64420HGT-K

HY57V64420HGT-H

HY57V64420HGT-P

HY57V64420HGT-S

HY57V64420HGLT-5/55/6/7

HY57V64420HGLT-K

HY57V64420HGLT-H

HY57V64420HGLT-P

HY57V64420HGLT-S

200/183/166/143MHz

133MHz

Normal

100MHz

4Banks x 4Mbits x4

LVTTL

400mil 54pin TSOP II

200/183/166/143MHz

133MHz

Low power

100MHz

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of

circuits described. No patent licenses are implied.

Rev. 0.4/Nov. 01

12 3 4 5 6 7...11

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与HY57V64420HGLT-55相关器件

型号	品牌	获取价格	描述	数据表
HY57V64420HGLT-6	HYNIX	获取价格	Synchronous DRAM, 16MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V64420HGLT-7	HYNIX	获取价格	Synchronous DRAM, 16MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V64420HGLT-H	HYNIX	获取价格	4 Banks x 4M x 4Bit Synchronous DRAM
HY57V64420HGLT-K	HYNIX	获取价格	4 Banks x 4M x 4Bit Synchronous DRAM
HY57V64420HGLT-P	HYNIX	获取价格	4 Banks x 4M x 4Bit Synchronous DRAM
HY57V64420HGLTP-55	HYNIX	获取价格	DRAM
HY57V64420HGLTP-6	HYNIX	获取价格	Synchronous DRAM, 16MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE
HY57V64420HGLTP-7	HYNIX	获取价格	Synchronous DRAM, 16MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE
HY57V64420HGLTP-H	HYNIX	获取价格	暂无描述
HY57V64420HGLTP-K	HYNIX	获取价格	暂无描述

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