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HY57V64420HGLTP-55 PDF预览

HY57V64420HGLTP-55

更新时间: 2024-11-30 14:38:03
品牌 Logo 应用领域
海力士 - HYNIX 动态存储器
页数 文件大小 规格书
11页 198K
描述
DRAM

HY57V64420HGLTP-55 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:,Reach Compliance Code:unknown
风险等级:5.84JESD-609代码:e6
端子面层:Tin/Bismuth (Sn/Bi)Base Number Matches:1

HY57V64420HGLTP-55 数据手册

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HY57V64420HGTP  
4 Banks x 4M x 4Bit Synchronous DRAM  
DESCRIPTION  
The Hynix HY57V64420HGTP is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which  
require large memory density and high bandwidth. HY57V64420HGTP is organized as 4banks of 4,194,304x4.  
HY57V644020HGTP is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are syn-  
chronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and out-  
put voltage levels are compatible with LVTTL.  
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by  
a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read  
or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or  
write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)  
FEATURES  
Single 3.3±0.3V power supply  
Auto refresh and self refresh  
All device pins are compatible with LVTTL interface  
4096 refresh cycles / 64ms  
JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin  
pitch  
Programmable Burst Length and Burst Type  
- 1, 2, 4, 8 or Full page for Sequential Burst  
- 1, 2, 4 or 8 for Interleave Burst  
Programmable CAS Latency ; 2, 3 Clocks  
Lead Free  
All inputs and outputs referenced to positive edge of system  
clock  
Data mask function by DQM  
Internal four banks operation  
ORDERING INFORMATION  
Part No.  
Clock Frequency  
Power  
Organization  
Interface  
Package  
HY57V64420HGTP-5/55/6/7  
HY57V64420HGTP-K  
HY57V64420HGTP-H  
HY57V64420HGTP-P  
HY57V64420HGTP-S  
HY57V64420HGLTP-5/55/6/7  
HY57V64420HGLTP-K  
HY57V64420HGLTP-H  
HY57V64420HGLTP-P  
HY57V64420HGLTP-S  
200/183/166/143MHz  
133MHz  
133MHz  
Normal  
100MHz  
100MHz  
4Banks x 4Mbits x4  
LVTTL  
400mil 54pin TSOP II  
200/183/166/143MHz  
133MHz  
133MHz  
Low power  
100MHz  
100MHz  
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of  
circuits described. No patent licenses are implied.  
Rev. 0.5 / Apr. 2004  
1

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