Datasheet > HY57V12420LT-8

HY57V12420LT-8

更新时间： 2024-10-31 23:57:11

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
12页	162K
描述
x4 SDRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

HY57V12420LT-8 数据手册

HY57V12420(L)T

4 Banks x 32M x 4Bit Synchronous DRAM

DESCRIPTION

The HY57V12420 is a 512-Mbit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large mem-

ory density and high bandwidth. HY57V12420 is organized as 4banks of 33,554,432x4.

HY57V12420 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized

with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage

levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by

a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or

write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or

write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3±0.3V power supply

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

8192 refresh cycles / 64ms

JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin

pitch

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

•

All inputs and outputs referenced to positive edge of system

clock

•

Data mask function by DQM

Internal four banks operation

•

Programmable CAS Latency ; 2, 3 Clocks

ORDERING INFORMATION

Part No.

Clock Frequency

Power

Organization

Interface

Package

HY57V12420T-6

HY57V12420T-K

HY57V12420T-H

HY57V12420T-8

HY57V12420T-P

HY57V12420T-S

HY57V12420LT-6

HY57V12420LT-K

HY57V12420LT-H

HY57V12420LT-8

HY57V12420LT-P

HY57V12420LT-S

166MHz

133MHz

125MHz

100MHz

166MHz

133MHz

125MHz

100MHz

Normal

4Banks x 32Mbits x 4

LVTTL

400mil 54pin TSOP II

Low power

This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev. 0.2/Dec. 01

12 3 4 5 6 7...12

中文翻译

下载PDF

与HY57V12420LT-8相关器件

型号	品牌	获取价格	描述	数据表
HY57V12420LT-H	ETC	获取价格	SDRAM\|4X32MX4\|CMOS\|TSOP\|54PIN\|PLASTIC
HY57V12420LT-K	HYNIX	获取价格	Synchronous DRAM, 128MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V12420LT-P	HYNIX	获取价格	Synchronous DRAM, 128MX4, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V12420LT-S	HYNIX	获取价格	Synchronous DRAM, 128MX4, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V12420T-6	HYNIX	获取价格	Synchronous DRAM, 128MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V12420T-8	HYNIX	获取价格	Synchronous DRAM, 128MX4, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V12420T-H	HYNIX	获取价格	Synchronous DRAM, 128MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V12420T-K	HYNIX	获取价格	Synchronous DRAM, 128MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V12420T-P	HYNIX	获取价格	Synchronous DRAM, 128MX4, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V12420T-S	HYNIX	获取价格	Synchronous DRAM, 128MX4, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54

与HY57V12420LT-8相关文章

三星深化印度制造布局，供应链本地化进程加速
2024-10-29

22
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

23
纳微科技震撼发布GaNSlim革新氮化镓功率芯片
2024-10-18

46
意法半导体发布第四代SiC技术，助力电动汽车电驱
2024-10-15

54

产品中心

服务支持

精选活动

关于我们

帮助中心

HY57V12420LT-8

HY57V12420LT-8 数据手册

与HY57V12420LT-8相关器件

与HY57V12420LT-8相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

HY57V12420LT-8

HY57V12420LT-8 数据手册

与HY57V12420LT-8相关器件

与HY57V12420LT-8相关文章

您还可以找

您在本页遇到什么问题？