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HY57V1291620TC-10P PDF预览

HY57V1291620TC-10P

更新时间: 2024-02-19 09:14:43
品牌 Logo 应用领域
其他 - ETC 内存集成电路光电二极管动态存储器时钟
页数 文件大小 规格书
13页 153K
描述
x16 SDRAM

HY57V1291620TC-10P 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:TSOP2, TSOP54,.46,32
针数:54Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.86访问模式:FOUR BANK PAGE BURST
最长访问时间:6 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):100 MHzI/O 类型:COMMON
交错的突发长度:1,2,4,8JESD-30 代码:R-PDSO-G54
JESD-609代码:e0长度:22.22 mm
内存密度:134217728 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:16功能数量:1
端口数量:1端子数量:54
字数:8388608 words字数代码:8000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:8MX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装等效代码:TSOP54,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
电源:3.3 V认证状态:Not Qualified
刷新周期:4096座面最大高度:1.2 mm
自我刷新:YES连续突发长度:1,2,4,8,FP
最大待机电流:0.0015 A子类别:DRAMs
最大压摆率:0.29 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL宽度:10.16 mm
Base Number Matches:1

HY57V1291620TC-10P 数据手册

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HY57V1291620  
4Banks x 2M x 16bits Synchronous DRAM  
DESCRIPTION  
The Hyundai HY57V1291620 is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory  
applications which require large memory density and high bandwidth. HY57V1291620 is organized as 4banks of  
2,097,152x16.  
HY57V1291620 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-  
puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very  
high bandwidth. All input and output voltage levels are compatible with LVTTL.  
Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or  
write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count  
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate  
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined  
design is not restricted by a `2N` rule.)  
FEATURES  
Single 3.3±0.3V power supply  
Auto refresh and self refresh  
All device pins are compatible with LVTTL interface  
4096 refresh cycles / 64ms  
JEDEC standard 400mil 54pin TSOP-II with 0.8mm  
of pin pitch  
Programmable Burst Length and Burst Type  
- 1, 2, 4, 8 and Full Page for Sequential Burst  
- 1, 2, 4 and 8 for Interleave Burst  
Programmable CAS Latency ; 2, 3 Clocks  
All inputs and outputs referenced to positive edge of  
system clock  
Data mask function by UDQM,LDQM  
Internal four banks operation  
ORDERING INFORMATION  
Part No.  
Clock Frequency  
Power  
Organization  
Interface  
Package  
HY57V1291620TC-75  
HY57V1291620TC-8  
133MHz  
125MHz  
100MHz  
100MHz  
100MHz  
133MHz  
125MHz  
100MHz  
100MHz  
100MHz  
HY57V1291620TC-10P  
HY57V1291620TC-10S  
HY57V1291620TC-10  
HY57V1291620LTC-75  
HY57V1291620LTC-8  
HY57V1291620LTC-10P  
HY57V1291620LTC-10S  
HY57V1291620LTC-10  
Normal  
4Banks x 2Mbits  
x16  
LVTTL  
400mil 54pin TSOP II  
Low Power  
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev. 1.0/Apr.99