Datasheet > HY57V1298020LTC-75

HY57V1298020LTC-75

更新时间： 2024-01-01 08:01:06

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
13页	151K
描述
x8 SDRAM

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HY57V1298020

4Banks x 4M x 8bits Synchronous DRAM

DESCRIPTION

The Hyundai HY57V1298020 is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory

applications which require large memory density and high bandwidth. HY57V1298020 is organized as 4banks of

4,194,304x8.

HY57V1298020 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-

puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very

high bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or

write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count

sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate

command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined

design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3±0.3V power supply

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

4096 refresh cycles / 64ms

JEDEC standard 400mil 54pin TSOP-II with 0.8mm

of pin pitch

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 and Full Page for Sequential Burst

- 1, 2, 4 and 8 for Interleave Burst

Programmable CAS Latency ; 2, 3 Clocks

•

All inputs and outputs referenced to positive edge of

system clock

•

Data mask function by DQM

Internal four banks operation

•

ORDERING INFORMATION

Part No.

Clock Frequency

Power

Organization

Interface

Package

HY57V1298020TC-75

HY57V1298020TC-8

133MHz

125MHz

100MHz

133MHz

125MHz

100MHz

HY57V1298020TC-10P

HY57V1298020TC-10S

HY57V1298020TC-10

HY57V1298020LTC-75

HY57V1298020LTC-8

HY57V1298020LTC-10P

HY57V1298020LTC-10S

HY57V1298020LTC-10

Normal

4Banks x 4Mbits

LVTTL

400mil 54pin TSOP II

Low Power

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 1.0/Apr.99

12 3 4 5 6 7...13

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与HY57V1298020LTC-75相关器件

型号	品牌	获取价格	描述	数据表
HY57V1298020LTC-8	HYNIX	获取价格	Synchronous DRAM, 16MX8, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V1298020TC-10	HYNIX	获取价格	Synchronous DRAM, 16MX8, 8ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V1298020TC-10P	HYNIX	获取价格	Synchronous DRAM, 16MX8, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V1298020TC-10S	HYNIX	获取价格	Synchronous DRAM, 16MX8, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V1298020TC-75	HYNIX	获取价格	Synchronous DRAM, 16MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V1298020TC-8	HYNIX	获取价格	Synchronous DRAM, 16MX8, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V161610ALTC-10	HYNIX	获取价格	Synchronous DRAM, 1MX16, 8ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50
HY57V161610ALTC-12	HYNIX	获取价格	Synchronous DRAM, 1MX16, 8.5ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50
HY57V161610ALTC-15	HYNIX	获取价格	Synchronous DRAM, 1MX16, 9ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50
HY57V161610ATC-10	HYNIX	获取价格	Synchronous DRAM, 1MX16, 8ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50

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