Datasheet > HY57V161610CLTC-10S

HY57V161610CLTC-10S

更新时间： 2023-01-02 20:52:55

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器光电二极管
页数	文件大小	规格书
11页	119K
描述
Synchronous DRAM, 1MX16, 6ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50

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HY57V161610C

2 Banks x 512K x 16 Bit Synchronous DRAM

DESCRIPTION

THE Hyundai HY57V161610C is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory

and graphic applications which require large memory density and high bandwidth. HY57V161610C is organized as

2banks of 524,288x16.

HY57V161610C is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are

synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band-

width. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 1,2, or 3), the number of consecutive read or

write cycles initiated by a single control command (Burst length of 1,2,4,8, or full page), and the burst count

sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate

command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipeline

design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3V ± 0.3V power supply

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

4096 refresh cycles / 64ms

JEDEC standard 400mil 50pin TSOP-II with 0.8mm

of pin pitch

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 and Full Page for Sequence Burst

- 1, 2, 4 and 8 for Interleave Burst

•

All inputs and outputs referenced to positive edge of

system clock

•

Programmable CAS Latency ; 1, 2, 3 Clocks

•

Data mask function by UDQM/LDQM

Internal two banks operation

ORDERING INFORMATION

Part No.

Clock Frequency

Organization

Interface

Package

HY57V161610CLTC-8

HY57V161610CLTC-10S

HY57V161610CLTC-10

125MHz

100MHz

400mil

50pin TSOP II

2Banks x 512Kbits x 16

LVTTL

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any

responsibility for use of circuits described. No patent licenses are implied

Rev. 2.0/Dec.98

12 3 4 5 6 7...11

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与HY57V161610CLTC-10S相关器件

型号	品牌	获取价格	描述	数据表
HY57V161610CLTC-8	HYNIX	获取价格	Synchronous DRAM, 1MX16, 6ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50
HY57V161610CTC-8	HYNIX	获取价格	Synchronous DRAM, 1MX16, 6ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50
HY57V161610D	HYNIX	获取价格	2 Banks x 512K x 16 Bit Synchronous DRAM
HY57V161610D-I	HYNIX	获取价格	2 Banks x 512K x 16 Bit Synchronous DRAM
HY57V161610DLTC-10P	HYNIX	获取价格	Synchronous DRAM, 1MX16, 6ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50
HY57V161610DTC	ETC	获取价格	1Mx16\|3.3V\|4K\|5\|SDR SDRAM - 16M
HY57V161610DTC-10	HYNIX	获取价格	2 Banks x 512K x 16 Bit Synchronous DRAM
HY57V161610DTC-10I	HYNIX	获取价格	2 Banks x 512K x 16 Bit Synchronous DRAM
HY57V161610DTC-10P	HYNIX	获取价格	Synchronous DRAM, 1MX16, 6ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50
HY57V161610DTC-15	HYNIX	获取价格	2 Banks x 512K x 16 Bit Synchronous DRAM

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