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HY57V161610DTC-I PDF预览

HY57V161610DTC-I

更新时间: 2024-02-20 09:49:31
品牌 Logo 应用领域
其他 - ETC 动态存储器
页数 文件大小 规格书
11页 122K
描述
1Mx16|3.3V|4K|55/6/7/10|SDR SDRAM - 16M

HY57V161610DTC-I 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:TSOP2, TSOP50,.46,32
针数:50Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.83访问模式:DUAL BANK PAGE BURST
最长访问时间:5.4 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):133 MHzI/O 类型:COMMON
交错的突发长度:1,2,4,8JESD-30 代码:R-PDSO-G50
JESD-609代码:e6长度:20.968 mm
内存密度:16777216 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:16功能数量:1
端口数量:1端子数量:50
字数:1048576 words字数代码:1000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:1MX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装等效代码:TSOP50,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified刷新周期:4096
座面最大高度:1.2 mm自我刷新:YES
连续突发长度:1,2,4,8,FP最大待机电流:0.002 A
子类别:DRAMs最大压摆率:0.11 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Bismuth (Sn/Bi)端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:10.16 mm
Base Number Matches:1

HY57V161610DTC-I 数据手册

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HY57V161610D-I  
2 Banks x 512K x 16 Bit Synchronous DRAM  
DESCRIPTION  
THE Hynix HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the Mobile applications  
which require low power consumption and industrial temperature range. HY57V161610D is organized as 2banks of  
524,288x16.  
HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are  
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band-  
width. All input and output voltage levels are compatible with LVTTL.  
Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or  
write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count  
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate  
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipeline  
design is not restricted by a `2N` rule.)  
FEATURES  
Auto refresh and self refresh  
Single 3.0V to 3.6V power supplyNote1)  
4096 refresh cycles / 64ms  
All device pins are compatible with LVTTL interface  
Programmable Burst Length and Burst Type  
- 1, 2, 4, 8 and Full Page for Sequence Burst  
- 1, 2, 4 and 8 for Interleave Burst  
Programmable CAS Latency ; 1, 2, 3 Clocks  
JEDEC standard 400mil 50pin TSOP-II with 0.8mm  
of pin pitch  
All inputs and outputs referenced to positive edge of  
system clock  
Data mask function by UDQM/LDQM  
Internal two banks operation  
ORDERING INFORMATION  
Part No.  
Clock Frequency  
Organization  
Interface  
Package  
HY57V161610DTC-55I  
HY57V161610DTC-6I  
HY57V161610DTC-7I  
HY57V161610DTC-10I  
183MHz  
166MHz  
143MHz  
100MHz  
400mil  
50pin TSOP II  
2Banks x 512Kbits x 16  
LVTTL  
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any  
responsibility for use of circuits described. No patent licenses are implied  
Rev. 0.3/Mar. 02  
1

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