HY57V161610ET-5

更新时间： 2024-01-24 20:24:19

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器
页数	文件大小	规格书
13页	182K
描述
2 Banks x 512K x 16 Bit Synchronous DRAM

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HY57V161610ET-5 数据手册

HY57V161610E

2 Banks x 512K x 16 Bit Synchronous DRAM

DESCRIPTION

THE Hynix HY57V161610E is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic appli-

cations which require large memory density and high bandwidth. HY57V161610E is organized as 2banks of 524,288x16.

HY57V161610E is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized

with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output

voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or write cycles initi-

ated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A

burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a

new burst read or write command on any cycle. (This pipeline design is not restricted by a `2N` rule.)

FEATURES

•

Auto refresh and self refresh

•

Single 3.0V to 3.6V power supply

4096 refresh cycles / 64ms

All device pins are compatible with LVTTL interface

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 and Full Page for Sequence Burst

- 1, 2, 4 and 8 for Interleave Burst

Programmable CAS Latency ; 1, 2, 3 Clocks

JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin

pitch

•

All inputs and outputs referenced to positive edge of system

clock

•

Data mask function by UDQM/LDQM

Internal two banks operation

ORDERING INFORMATION

Part No.

Clock Frequency

Organization

Interface

Package

HY57V161610ET-5

HY57V161610ET-55

HY57V161610ET-6

HY57V161610ET-7

HY57V161610ET-8

HY57V161610ET-10

HY57V161610ET-15

200MHz

183MHz

166MHz

143MHz

125MHz

100MHz

66MHz

400mil

50pin TSOP II

2Banks x 512Kbits x 16

LVTTL

Note :

1. VDD(min) of HY57V161610ET-5/55 is 3.15V

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for

use of circuits described. No patent licenses are implied

Rev. 0.2 / Aug. 2003

12 3 4 5 6 7...13

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HY57V161610ET-55	HYNIX	2 Banks x 512K x 16 Bit Synchronous DRAM	获取价格
HY57V161610ET-55I	HYNIX	2 Banks x 512K x 16 Bit Synchronous DRAM	获取价格
HY57V161610ET-5I	HYNIX	2 Banks x 512K x 16 Bit Synchronous DRAM	获取价格
HY57V161610ET-6	HYNIX	2 Banks x 512K x 16 Bit Synchronous DRAM	获取价格
HY57V161610ET-6I	HYNIX	2 Banks x 512K x 16 Bit Synchronous DRAM	获取价格
HY57V161610ET-7	HYNIX	2 Banks x 512K x 16 Bit Synchronous DRAM	获取价格