Datasheet > HY57V161610DTC-5

HY57V161610DTC-5

更新时间： 2024-02-25 22:26:39

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器
页数	文件大小	规格书
13页	183K
描述
2 Banks x 512K x 16 Bit Synchronous DRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

HY57V161610DTC-5 数据手册

HY57V161610D

2 Banks x 512K x 16 Bit Synchronous DRAM

DESCRIPTION

THE Hyundai HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic

applications which require large memory density and high bandwidth. HY57V161610D is organized as 2banks of 524,288x16.

HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized

with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output

voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or write cycles initi-

ated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A

burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a

new burst read or write command on any cycle. (This pipeline design is not restricted by a `2N` rule.)

FEATURES

•

Auto refresh and self refresh

•

Single 3.0V to 3.6V power supply

4096 refresh cycles / 64ms

All device pins are compatible with LVTTL interface

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 and Full Page for Sequence Burst

- 1, 2, 4 and 8 for Interleave Burst

Programmable CAS Latency ; 1, 2, 3 Clocks

JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin

pitch

•

All inputs and outputs referenced to positive edge of system

clock

•

Data mask function by UDQM/LDQM

Internal two banks operation

ORDERING INFORMATION

Part No.

Clock Frequency

Organization

Interface

Package

HY57V161610DTC-5

HY57V161610DTC-55

HY57V161610DTC-6

HY57V161610DTC-7

HY57V161610DTC-8

HY57V161610DTC-10

HY57V161610DTC-15

200MHz

183MHz

166MHz

143MHz

125MHz

100MHz

66MHz

400mil

50pin TSOP II

2Banks x 512Kbits x 16

LVTTL

Note :

1. VDD(min) of HY57V161610DTC-5/55 is 3.15V

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for

use of circuits described. No patent licenses are implied

Rev. 4.0/Aug. 02

12 3 4 5 6 7...13

中文翻译

下载PDF

与HY57V161610DTC-5相关器件

型号	品牌	获取价格	描述	数据表
HY57V161610DTC-55	HYNIX	获取价格	2 Banks x 512K x 16 Bit Synchronous DRAM
HY57V161610DTC-55I	HYNIX	获取价格	2 Banks x 512K x 16 Bit Synchronous DRAM
HY57V161610DTC-6	HYNIX	获取价格	2 Banks x 512K x 16 Bit Synchronous DRAM
HY57V161610DTC-6I	HYNIX	获取价格	2 Banks x 512K x 16 Bit Synchronous DRAM
HY57V161610DTC-7	HYNIX	获取价格	2 Banks x 512K x 16 Bit Synchronous DRAM
HY57V161610DTC-7I	HYNIX	获取价格	2 Banks x 512K x 16 Bit Synchronous DRAM
HY57V161610DTC-8	HYNIX	获取价格	2 Banks x 512K x 16 Bit Synchronous DRAM
HY57V161610DTC-I	ETC	获取价格	1Mx16\|3.3V\|4K\|55/6/7/10\|SDR SDRAM - 16M
HY57V161610E	HYNIX	获取价格	2 Banks x 512K x 16 Bit Synchronous DRAM
HY57V161610ET-10	HYNIX	获取价格	2 Banks x 512K x 16 Bit Synchronous DRAM

与HY57V161610DTC-5相关文章

BSS138LT3G：一款高效能N沟道MOSFET的全面解析
2024-07-04

4
解读EGP10B二极管资料手册：产品特性、参数分析
2024-07-04

3
RT9164AGG手册资料详解：引脚信息、设计指南
2024-07-04

3
2SA1037KPT资料详解：产品特性、电气参数、设计指南
2024-07-04

5

产品中心

服务支持

精选活动

关于我们

帮助中心

HY57V161610DTC-5

HY57V161610DTC-5 数据手册

与HY57V161610DTC-5相关器件

与HY57V161610DTC-5相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

HY57V161610DTC-5

HY57V161610DTC-5 数据手册

与HY57V161610DTC-5相关器件

与HY57V161610DTC-5相关文章

您还可以找

您在本页遇到什么问题？