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HY29F040P-90E PDF预览

HY29F040P-90E

更新时间: 2024-11-06 14:28:15
品牌 Logo 应用领域
海力士 - HYNIX 光电二极管内存集成电路
页数 文件大小 规格书
40页 504K
描述
Flash, 512KX8, 90ns, PDIP32, PLASTIC, DIP-32

HY29F040P-90E 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:PLASTIC, DIP-32针数:32
Reach Compliance Code:unknownECCN代码:3A001.A.2.C
HTS代码:8542.32.00.51风险等级:5.58
最长访问时间:90 ns其他特性:MINIMUM 100000 PROGRAM/ERASE CYCLES
JESD-30 代码:R-PDIP-T32长度:42.164 mm
内存密度:4194304 bit内存集成电路类型:FLASH
内存宽度:8功能数量:1
端子数量:32字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:512KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL编程电压:5 V
认证状态:Not Qualified座面最大高度:5.715 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL类型:NOR TYPE
宽度:15.24 mmBase Number Matches:1

HY29F040P-90E 数据手册

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HY29F040 Series  
512K x 8-bit CMOS, 5.0 Volt-only, Sector Erase Flash Memory  
KEY FEATURES  
Sector Protection  
5.0 V ± 10% Read, Program, and Erase  
- Minimizes system-level power requirements  
High performance  
- 90 ns access time  
Low Power Consumption  
- 20 mA typical active read current  
- 30 mA typical program/erase current  
Compatible with the JEDEC Standard for  
Single-Voltage Flash Memories  
- Uses software commands, pinouts, and  
packages following the industry standards  
for single power supply Flash memories  
- Superior inadvertent write protection  
Flexible Sector Architecture  
- Any sector may be locked to prevent any  
program or erase operation within that sector  
Erase Suspend/Resume  
- Suspends a sector erase operation to allow  
data to be read from, or programmed into,  
any sector not being erased  
- The erase operation can then be resumed  
Internal Erase Algorithm  
- Automatically erases a sector, any combination  
of sectors, or the entire chip  
Internal Programming Algorithm  
- Automatically programs and verifies data at a  
specified address  
- Eight equal size sectors of 64K bytes each  
- Any combination of sectors can be erased  
concurrently  
Minimum 100,000 Program/Erase Cycles  
PLCC, PDIP and TSOP Packages  
- Supports full chip erase  
DESCRIPTION  
latch addresses and data needed for the pro-  
gramming and erase operations.  
The HY29F040 is a 4 Megabit, 5.0 volt-only, CMOS  
Flash memory device organized as 524,288  
(512 K) bytes of 8 bits each. The Flash memory  
array is organized into eight uniform-sized sec-  
tors of 64 Kbytes each. The device is offered  
with access times of 90, 120 and 150 ns and is  
provided in standard 32-pin PDIP, PLCC and  
TSOP packages. It is designed to be pro-  
grammed and erased in-system with a 5.0 volt  
power-supply and can also be reprogrammed  
in standard PROM programmers.  
The HY29F040 is programmed by invoking the  
program command sequence. This starts the  
internal byte programming algorithm that auto-  
matically times the program pulse width and  
verifies the proper cell margin. An erase opera-  
tion is performed likewise, by invoking the sec-  
tor erase or chip erase command sequence.  
This starts the internal erasing algorithm that  
automatically preprograms the sector (if it is not  
already programmed), times the erase pulse  
width and verifies the proper cell margin. Sec-  
tors of the HY29F040 Flash memory array are  
electrically erased via Fowler-Nordheim tunnel-  
ing. Bytes are programmed one byte at a time  
using a hot electron injection mechanism.  
The HY29F040 has separate chip enable (/CE),  
write enable (/WE) and output enable (/OE) con-  
trols. Hyundai Flash memory devices reliably  
store memory data even after 100,000 program/  
erase cycles.  
The device is entirely pin and command set  
compatible with the JEDEC standard for 4 Mega-  
bit Flash memory devices. Commands are writ-  
ten to an internal command register using stan-  
dard microprocessor write timings. Register  
contents serve as inputs to an internal state-  
machine which controls the erase and pro-  
gramming circuitry. Write cycles also internally  
The HY29F040 features a flexible sector erase  
architecture. The device memory array is divided  
into eight sectors of 64K bytes each. The sec-  
tors can be erased individually or in groups with-  
out affecting the data in other sectors. The mul-  
tiple sector erase and full chip erase capabili-  
ties provide flexibility in altering the data in the  
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of  
circuits described. No patent licences are implied.  
Rev.04: April 1998  
Hyundai Semiconductor  

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