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HX318C9T3K2-8 PDF预览

HX318C9T3K2-8

更新时间: 2024-11-25 01:20:47
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其他 - ETC 双倍数据速率
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2页 884K
描述
DDR3-1866 CL9 240-Pin DIMM Kit

HX318C9T3K2-8 数据手册

 浏览型号HX318C9T3K2-8的Datasheet PDF文件第2页 
HX318C9T3K2/8  
8GB (4GB 512M x 64-Bit x 2 pcs.)  
DDR3-1866 CL9 240-Pin DIMM Kit  
SPECIFICATIONS  
CL(IDD)  
11 cycles  
Row Cycle Time (tRCmin)  
48.125ns (min.)  
260ns (min.)  
Refresh to Active/Refresh  
Command Time (tRFCmin)  
Row Active Time (tRASmin)  
Maximum Operating Power  
UL Rating  
35ns (min.)  
TBD W* (per module)  
94 V - 0  
Operating Temperature  
Storage Temperature  
0o C to 85o C  
-55o C to +100o C  
*Power will vary depending on the SDRAM used.  
DESCRIPTION  
FEATURES  
HyperX HX318C9T3K2/8 is a kit of two 512M x 64-bit (4GB)  
DDR3-1866 CL9 SDRAM (Synchronous DRAM), 1Rx8  
memory modules, based on eight 512M x 8-bit FBGA  
components per module. Each module kit supports Intel®  
XMP (Extreme Memory Profiles). Total kit capacity is 8GB.  
Each module kit has been tested to run at DDR3-1866 at a  
low latency timing of 9-10-11 at 1.5V. The SPDs are  
programmed to JEDEC standard latency DDR3-1600 timing of  
11-11-11 at 1.5V. Each 240-pin DIMM uses gold contact  
fingers. The JEDEC standard electrical and mechanical  
specifications are as follows:  
JEDEC standard 1.5V (1.425V ~ 1.575V) Power Supply  
VDDQ = 1.5V (1.425V ~ 1.575V)  
800MHz fCK for 1600Mb/sec/pin  
8 independent internal bank  
Programmable CAS Latency: 11, 10, 9, 8, 7, 6  
Programmable Additive Latency: 0, CL - 2, or CL - 1 clock  
8-bit pre-fetch  
Burst Length: 8 (Interleave without any limit, sequential with  
starting address “000” only), 4 with tCCD = 4 which does not  
allow seamless read or write [either on the fly using A12 or  
MRS]  
Bi-directional Differential Data Strobe  
XMP TIMING PARAMETERS  
Internal(self) calibration : Internal self calibration through ZQ  
JEDEC: DDR3-1600 CL11-11-11 @1.5V  
XMP Profile #1: DDR3-1866 CL9-10-11 @1.5V  
XMP Profile #2: DDR3-1600 CL9-9-9 @1.5V  
pin (RZQ : 240 ohm ± 1%)  
On Die Termination using ODT pin  
Average Refresh Period 7.8us at lower than TCASE 85°C,  
3.9us at 85°C < TCASE < 95°C  
Asynchronous Reset  
Height 1.827” (46.41mm) w/ heatsink, single sided  
component  
Continued >>  
kingston.com/hyperx  
Document No. 4807094-001.A00 07/23/14 Page 1  

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