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HMD2M64B2-8 PDF预览

HMD2M64B2-8

更新时间: 2024-11-09 03:01:19
品牌 Logo 应用领域
HANBIT 动态存储器
页数 文件大小 规格书
10页 75K
描述
Synchronous DRAM Module 16Mbyte (2Mx64-Bit), SO-DIMM, 4Banks, 4K Ref., 3.3V

HMD2M64B2-8 数据手册

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HANBit  
HSD2M64B2  
Synchronous DRAM Module 16Mbyte (2Mx64-Bit), SO-DIMM,  
4Banks, 4K Ref., 3.3V  
Part No. HSD2M64B2  
GENERAL DESCRIPTION  
The HSD2M64B2 is a 2M x 64 bit Synchronous Dynamic RAM high density memory module. The module consists of  
two CMOS 512K x 32 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 144-pin glass-epoxy  
substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The  
HSD2M64B2 is a SO-DIMM(Small Outline Dual in line Memory Module) and is intended for mounting into 144-pin edge  
connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are  
possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be  
useful for a variety of high bandwidth, high performance memory system applications All module components may be  
powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.  
FEATURES  
Part Identification  
HSD2M64B2-F/10 :100MHz  
HSD2M64B2-F/8 :125MHz  
* F : Auto Self-Refresh with Low Power  
Burst mode operation  
Auto & self refresh capability (4096 Cycles/64ms)  
LVTTL compatible inputs and outputs  
Single 3.3V ±0.3V power supply  
MRS cycle with address key programs  
- Latency (Access from column address)  
- Burst length (1, 2, 4, 8 & Full page)  
- Data scramble (Sequential & Interleave)  
JEDEC standard 144-Pin SO-DIMM  
All inputs are sampled at the positive going edge of the system clock  
The used device is 512Kx32Bitx4Banks SDRAM  
URL:www.hbe.co.kr  
REV.1.0 (August.2002)  
HANBit Electronics Co.,Ltd.  
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