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HM5264405LTT-B60 PDF预览

HM5264405LTT-B60

更新时间: 2024-10-27 23:56:15
品牌 Logo 应用领域
其他 - ETC 内存集成电路光电二极管动态存储器时钟
页数 文件大小 规格书
67页 787K
描述
x4 SDRAM

HM5264405LTT-B60 数据手册

 浏览型号HM5264405LTT-B60的Datasheet PDF文件第2页浏览型号HM5264405LTT-B60的Datasheet PDF文件第3页浏览型号HM5264405LTT-B60的Datasheet PDF文件第4页浏览型号HM5264405LTT-B60的Datasheet PDF文件第5页浏览型号HM5264405LTT-B60的Datasheet PDF文件第6页浏览型号HM5264405LTT-B60的Datasheet PDF文件第7页 
HM5264165-B60  
HM5264805-B60  
HM5264405-B60  
64M LVTTL interface SDRAM  
100 MHz  
1-Mword × 16-bit × 4-bank/2-Mword × 8-bit × 4-bank  
/4-Mword × 4-bit × 4-bank  
PC/100 SDRAM  
ADE-203-832D (Z)  
Rev. 2.0  
Oct. 20, 1998  
Description  
The Hitachi HM5264165 is a 64-Mbit SDRAM organized as 1048576-word × 16-bit × 4 bank. The Hitachi  
HM5264805 is a 64-Mbit SDRAM organized as 2097152-word × 8-bit × 4 bank. The Hitachi HM5264405  
is a 64-Mbit SDRAM organized as 4194304-word × 4-bit × 4 bank. All inputs and outputs are referred to  
the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.  
Features  
3.3 V power supply  
Clock frequency: 100 MHz (max)  
LVTTL interface  
Single pulsed RAS  
4 banks can operate simultaneously and independently  
Burst read/write operation and burst read/single write operation capability  
Programmable burst length: 1/2/4/8/full page  
2 variations of burst sequence  
Sequential (BL = 1/2/4/8/full page)  
Interleave (BL = 1/2/4/8)  
Programmable CAS latency: 2/3  
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