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HM5264805DTT-80 PDF预览

HM5264805DTT-80

更新时间: 2024-10-28 20:29:19
品牌 Logo 应用领域
日立 - HITACHI 时钟动态存储器光电二极管内存集成电路
页数 文件大小 规格书
60页 583K
描述
Synchronous DRAM, 8MX8, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54

HM5264805DTT-80 数据手册

 浏览型号HM5264805DTT-80的Datasheet PDF文件第2页浏览型号HM5264805DTT-80的Datasheet PDF文件第3页浏览型号HM5264805DTT-80的Datasheet PDF文件第4页浏览型号HM5264805DTT-80的Datasheet PDF文件第5页浏览型号HM5264805DTT-80的Datasheet PDF文件第6页浏览型号HM5264805DTT-80的Datasheet PDF文件第7页 
HM5264165D Series  
HM5264805D Series  
HM5264405D Series  
64M LVTTL interface SDRAM  
125 MHz  
1-Mword × 16-bit × 4-bank/2-Mword × 8-bit × 4-bank/  
4-Mword × 4-bit × 4-bank  
ADE-203-910A (Z)  
Rev. 1.0  
Dec. 2, 1998  
Description  
The Hitachi HM5264165D is a 64-Mbit SDRAM organized as 1048576-word × 16-bit × 4 bank. The  
Hitachi HM5264805D is a 64-Mbit SDRAM organized as 2097152-word × 8-bit × 4 bank. The Hitachi  
HM5264405D is a 64-Mbit SDRAM organized as 4194304-word × 4-bit × 4 bank. All inputs and outputs  
are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.  
Features  
3.3 V power supply  
Clock frequency: 125 MHz (max)  
LVTTL interface  
Single pulsed RAS  
4 banks can operate simultaneously and independently  
Burst read/write operation and burst read/single write operation capability  
Programmable burst length: 1/2/4/8/full page  
2 variations of burst sequence  
Sequential (BL = 1/2/4/8/full page)  
Interleave (BL = 1/2/4/8)  
Programmable CAS latency: 2/3  
Byte control by DQM : DQM (HM5264805D/HM5264405D)  
: DQMU/DQML (HM5264165D)  
Refresh cycles: 4096 refresh cycles/64 ms  
2 variations of refresh  
Auto refresh  
Self refresh  

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