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HIP6501EVAL1

更新时间: 2024-09-20 22:09:43
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英特矽尔 - INTERSIL 控制器
页数 文件大小 规格书
14页 143K
描述
Triple Linear Power Controller with ACPI Control Interface

HIP6501EVAL1 数据手册

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HIP6501A  
Data Sheet  
February 2000  
File Number 4749.2  
Triple Linear Power Controller with ACPI  
Control Interface  
Features  
• Provides 3 ACPI-Controlled Voltages  
The HIP6501A, paired with either the HIP6020 or HIP6021,  
simplifies the implementation of ACPI-compliant designs in  
microprocessor and computer applications. The IC  
integrates two linear controllers and a low-current pass  
transistor, as well as the monitoring and control functions  
into a 16-pin SOIC package. One linear controller generates  
- 5V Active/Sleep (5V  
DUAL  
)
- 3.3V Active/Sleep (3.3V  
)
DUAL  
- 2.5V/3.3V Active/Sleep (2.5V  
)
MEM  
• Simple Control Design - No Compensation Required  
• Excellent Output Voltage Regulation  
the 3.3V  
voltage plane from an ATX power supply’s  
- 3.3V  
DUAL  
States Only  
Output: ±2.0% Over Temperature; Sleep  
DUAL  
5VSB output during sleep states (S3, S4/S5), powering the  
PCI slots through an external pass transistor, as instructed  
- 2.5V/3.3V Output: ±2.0% Over Temperature; Both  
by the status of the 3.3V  
enable pin. An additional pass  
Operational States (3.3V setting in sleep only)  
DUAL  
transistor is used to switch in the ATX 3.3V output for PCI  
operation during S0 and S1 (active) operatingstates. The  
second linear controller supplies the computer system’s  
2.5V/3.3V memory power through an external pass  
transistor in active states. During S3 state, an integrated  
pass transistor supplies the 2.5V/3.3V sleep-state power. A  
• Fixed Output Voltages Require No Precision External  
Resistors  
• Small Size  
- Small External Component Count  
• Selectable 2.5V  
MEM  
Output Voltage Via FAULT/MSEL Pin  
third controller powers up a 5V  
plane by switching in  
DUAL  
- 2.5V for RDRAM Memory  
- 3.3V for SDRAM Memory  
the ATX 5V output in active states, or the ATX 5VSB in sleep  
states.  
• Under-Voltage Monitoring of All Outputs with Centralized  
FAULT Reporting  
The HIP6501A’s operating mode (active-state outputs or  
sleep-state outputs) is selectable through two control pins:  
S3 and S5. Further control of the logic governing activation  
of different power modes is offered through two enabling  
• Adjustable Soft-Start Function Eliminates 5VSB  
Perturbations  
pins: EN3VDL and EN5VDL. In active states, the 3.3V  
DUAL  
Pinout  
linear regulator uses an external N-Channel pass MOSFET  
to connect the output (V ) directly to the 3.3V input  
HIP6501A (SOIC)  
OUT1  
supplied by an ATX (or equivalent) power supply, while  
incurring minimal losses. In sleep state, the 3.3V output  
TOP VIEW  
DUAL  
16  
1
2
3
4
5
6
7
8
VSEN2  
5VSB  
EN3VDL  
3V3DLSB  
is supplied from the ATX 5VSB through an NPN transistor,  
also external to the controller. Active state power delivery for  
15 DRV2  
14  
12V  
the 2.5/3.3V  
output is done through an external NPN  
MEM  
13  
SS  
3V3DL  
transistor, or an NMOS switch for the 3.3V setting. In sleep  
states, conduction on this output is transferred to an internal  
12 5VDL  
EN5VDL  
S3  
5VDLSB  
11  
10  
9
pass transistor. The 5V  
output is powered through two  
DUAL  
DLA  
S5  
external MOS transistors. In sleep states, a PMOS (or PNP)  
transistor conducts the current from the ATX 5VSB output,  
while in active states, current flow is transferred to an NMOS  
transistor connected to the ATX 5V output. Similar to the  
GND  
FAULT/MSEL  
3.3V  
output, the operation of the 5V output is  
DUAL  
DUAL  
dictated not only by the status of the S3 and S5 pins, but that  
of the EN5VDL pin as well.  
Ordering Information  
TEMP.  
PKG.  
NO.  
o
PART NUMBER RANGE ( C)  
PACKAGE  
16 Ld SOIC  
HIP6501ACB  
0 to 70  
M16.15  
HIP6501EVAL1  
Evaluation Board  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 2000  
1

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