HIP6503
TM
Data Sheet
June 2000
File Number 4882.1
Multiple Linear Power Controller with
ACPI Control Interface
Features
• Provides 5 ACPI-Controlled Voltages
- 5V USB/Keyboard/Mouse (Active/Sleep)
The HIP6503 complements either an HIP6020 or an
HIP6021 in ACPI-compliant designs for microprocessor and
computer applications. The IC integrates four linear
controllers/regulators, switching, monitoring and control
functions into a 20 pin SOIC package. One linear controller
DUAL
- 3.3V
- 2.5V
- 2.5V
/3.3V PCI/Auxiliary/LAN (Active/Sleep)
SB
DUAL
RDRAM or 3.3V
MEM
SDRAM (Active/Sleep)
MEM
Clock/Processor Terminations (Active Only)
CLK
- 1.8V ICH2 Resume
SB
generates the 3.3V
/3.3V voltage plane from the ATX
DUAL
SB
• Excellent Output Voltage Regulation
supply’s 5VSB output, powering the south bridge and the
PCI slots through an external pass transistor during sleep
states (S3, S4/S5). A second transistor is used to switch in
the ATX 3.3V output for operation during S0 and S1/S2
(active) operating states. A linear controllers/regulator
supplies at choice either of 2.5V or 3.3V memory power
through external pass transistors (switch for 3.3V setting) in
active states. During sleep states, integrated pass
- 3.3V
/3.3V Output: ±2.0% Over Temperature;
SB
DUAL
Sleep State Only
- 2.5V /3.3V
Output: ±2.0% Over Temperature;
Both Operational States (3.3V in sleep only)
MEM MEM
MEM
Outputs: ±2.0% Over Temperature
- 1.8V , 2.5V
SB
CLK
• Small Size
- Very Low External Component Count
transistors supply the sleep power. Another controller
• Dual Memory Voltage Selection Via FAULT/MSEL Pin
- 2.5V for RDRAM Memory
powers up the 5V
plane by switching in the ATX 5V
DUAL
output in active states, and the ATX 5VSB in sleep states.
Two internal regulators output both a dedicated, noise-free
2.5V clock chip supply, as well as a 1.8V ICH2 resume well
voltage. The HIP6503’s operating mode (active outputs or
sleep outputs) is selectable through two digital control pins,
- 3.3V for SDRAM Memory
• Undervoltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
S3 and S5. Enabling sleep state support on the 5V
output is offered through the EN5VDL pin. In active state, the
Applications
DUAL
•
Motherboard Power Regulation for ACPI-Compliant
Computers
3.3V
/3.3V and 2.5V
/3.3V linear regulators
DUAL
SB
MEM
MEM
use external N-channel pass MOSFETs to connect the
outputs directly to the 3.3V input supplied by an ATX power
supply, for minimal losses. In sleep state, power delivery on
both outputs is transferred to NPN transistors - external to
Pinout
HIP6503
(SOIC)
TOP VIEW
the controller on the 3.3V
/3.3V , internal on the
DUAL
SB
2.5V
/3.3V
. Active state regulation on the 2.5V
MEM
MEM
MEM
output is performed through an external NPN transistor. The
20
1
2
VSEN2
5VSB
1V8IN
1V8SB
5V output is powered through two external MOS
DUAL
19 DRV2
transistors. In sleep states, a PMOS (or PNP) transistor
conducts the current from the ATX 5VSB output; while in
active state, current flow is transferred to an NMOS
transistor connected to the ATX 5V output. The operation of
18
17
3
5V
12V
3V3DLSB
3V3DL
VCLK
4
16 SS
5
5VDL
15
14
6
the 5V
output is dictated not only by the status of the
DUAL
S3 and S5 pins, but that of the EN5VDL pin as well. The
3.3V /3.3V and 1.8V outputs are active for as long
5VDLSB
3V3
7
EN5VDL
13 DLA
8
DUAL SB SB
as the ATX 5VSB voltage is applied to the chip. The 2.5V
output is only active during S0 and S1/S2, and uses the 3V3
pin as input source for its internal pass element.
12
11
9
FAULT/MSEL
GND
CLK
S3
S5
10
Ordering Information
TEMP.
PKG.
NO.
o
PART NUMBER RANGE ( C)
PACKAGE
20 Ld SOIC
HIP6503CB
0 to 70
M20.3
HIP6503EVAL1
Evaluation Board
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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