HIP6502
Data Sheet
December 1999
File Number 4775.1
Multiple Linear Power Controller with
ACPI Control Interface
Features
• Provides 5 ACPI-Controlled Voltages
- 5V USB/Keyboard/Mouse (Active/Sleep)
The HIP6502 complements either an HIP6020 or an
HIP6021 in ACPI-compliant designs for microprocessor and
computer applications. The IC integrates four linear
controllers/regulators, switching, monitoring and control
functions into a 20-pin SOIC package. One linear controller
DUAL
- 3.3V
- 2.5V
- 3.3V
- 2.5V
/3.3V PCI/Auxiliary/LAN (Active/Sleep)
SB
RDRAM (Active/Sleep)
SDRAM (Active/Sleep)
DUAL
MEM
MEM
Clock/Processor Terminations (Active Only)
CLK
generates the 3.3V
/3.3V voltage plane from the ATX
DUAL
SB
• Excellent Output Voltage Regulation
- 3.3V /3.3V Output: ±2.0% Over Temperature;
supply’s 5VSB output, powering the south bridge and the
PCI slots through an external pass transistor during sleep
states (S3, S4/S5). A second transistor is used to switch in
the ATX 3.3V output for operation during S0 and S1/S2
(active) operating states. Two linear controllers/regulators
supply a choice of either or both of the computer system’s
2.5V or 3.3V memory power through external pass
DUAL SB
Sleep State Only
- 2.5V and 3.3V
Output: ±2.0% Over
MEM
MEM
Temperature; Both Operational States (3.3V
sleep only)
in
MEM
- 2.5V
Output: ±2.0% Over Temperature
CLK
transistors in active states. During sleep states, integrated
pass transistors supply the sleep power. Another controller
• Small Size
- Very Low External Component Count
powers up the 5V
plane by switching in the ATX 5V
DUAL
• Dual Memory Voltage Support Via MSEL Pin
- 2.5V for RDRAM Memory
output in active states, and the ATX 5VSB in sleep states.
One internal regulator outputs a dedicated, noise-free 2.5V
clock chip supply. The HIP6502’s operating mode (active
outputs or sleep outputs) is selectable through two digital
control pins, S3 and S5. Enabling sleep state support on the
- 3.3V for SDRAM Memory
- Both 2.5V and 3.3V for Flexible Systems
• Under-Voltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
5V
output is offered through the EN5VDL pin. In active
DUAL
state, the 3.3V
and 3.3V
linear regulators use
DUAL
MEM
external N-channel pass MOSFETs to connect the outputs
directly to the 3.3V input supplied by an ATX (or equivalent)
power supply, for minimal losses. In sleep state, power
delivery on both outputs is transferred to NPN transistors -
Applications
•
Motherboard Power Regulation for ACPI-Compliant
Computers
external to the controller on the 3.3V
, internal on the
DUAL
Pinout
3.3V
. Active state regulation on the 2.5V
output is
MEM
MEM
HIP6502
(SOIC)
TOP VIEW
performed through an external NPN transistor. In sleep
state, conduction on this output is transferred to an internal
pass transistor. The 5V
output is powered through two
DUAL
external MOS transistors. In sleep states, a PMOS (or PNP)
transistor conducts the current from the ATX 5VSB output;
while in active state, current flow is transferred to an NMOS
transistor connected to the ATX 5V output. The operation of
20
1
2
MSEL
VSEN2
5VSB
19 DRV2
VSEN1
18
17
3
5V
the 5V
output is dictated not only by the status of the
4
12V
3V3DLSB
3V3DL
VCLK
DUAL
S3 and S5 pins, but that of the EN5VDL pin as well. The
3.3V /3.3V output is active for as long as the ATX
16 SS
5
5VDL
15
14
6
DUAL SB
5VSB voltage is applied to the chip. The 2.5V
output is
CLK
5VDLSB
3V3
7
only active during S0 and S1/S2, and uses the 3V3 pin as
input source for its internal pass element.
EN5VDL
13 DLA
8
12
11
9
FAULT
GND
S3
S5
10
Ordering Information
TEMP.
PKG.
NO.
o
PART NUMBER RANGE ( C)
PACKAGE
20 Ld SOIC
HIP6502CB
0 to 70
M20.3
HIP6502EVAL1
Evaluation Board
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
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