HIP6503
®
Data Sheet
July 21, 2005
FN4882.5
Multiple Linear Power Controller with
ACPI Control Interface
Features
• Provides 5 ACPI-Controlled Voltages
- 5V USB/Keyboard/Mouse
The HIP6503 complements either an HIP6020 or an
HIP6021 in ACPI-compliant designs for microprocessor and
computer applications. The IC integrates four linear
controllers/regulators, switching, monitoring and control
functions into a 20 pin SOIC package. One linear controller
DUAL
- 3.3V
- 2.5V
- 2.5V
/3.3V PCI/Auxiliary/LAN
DUAL
MEM
CLK
SB
RDRAM or 3.3V
Clock/Processor Terminations
SDRAM
MEM
- 1.8V ICH2 Resume Well
SB
generates the 3.3V
/3.3V voltage plane from the ATX
DUAL SB
• Excellent Output Voltage Regulation
supply’s 5VSB output, powering the south bridge and the
PCI slots through an external pass transistor during sleep
states (S3, S4/S5). A second transistor is used to switch in
the ATX 3.3V output for operation during S0 and S1/S2
(active) operating states. A linear controllers/regulator
supplies at choice either of 2.5V or 3.3V memory power
through external pass transistors (switch for 3.3V setting) in
active states. During sleep states, integrated pass
- All Outputs: ±2.0% Over Temperature (as applicable)
• Small Size; Very Low External Component Count
• RDRAM/SDRAM/DDRAM Memory Support
• Undervoltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
• Pb-Free Plus Anneal Available (RoHS Compliant)
transistors supply the sleep power. Another controller
Applications
powers up the 5V
plane by switching in the ATX 5V
DUAL
•
ACPI-Compliant Power Regulation for Motherboards
output in active states, and the ATX 5VSB in sleep states.
Two internal regulators output both a dedicated, noise-free
2.5V clock chip supply, as well as a 1.8V ICH2 resume well
voltage. The HIP6503’s operating mode (active outputs or
sleep outputs) is selectable through two digital control pins,
Ordering Information
TEMP.
PKG.
PART NUMBER
HIP6503CB
RANGE (°C)
0 to 70
PACKAGE
20 Ld SOIC
DWG. #
S3 and S5. Enabling sleep state support on the 5V
DUAL
M20.3
output is offered through the EN5VDL pin. In active state, the
3.3V /3.3V and 2.5V /3.3V linear regulators
HIP6503CBZ (Note)
0 to 70
20 Ld SOIC (Pb-free) M20.3
DUAL
SB MEM
MEM
HIP6503CBZ-T (Note) 20 Ld SOIC Tape and Reel
(Pb-free)
M20.3
use external N-channel pass MOSFETs to connect the
outputs directly to the 3.3V input supplied by an ATX power
supply, for minimal losses. In sleep state, power delivery on
both outputs is transferred to NPN transistors. Active state
HIP6503EVAL1
Evaluation Board
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
regulation on the 2.5V
output is performed through an
MEM
external NPN transistor. The 5V
output is powered
DUAL
through two external MOS transistors. In sleep states, a
PMOS (or PNP) transistor conducts the current from the ATX
5VSB output; while in active state, current flow is transferred
to an NMOS transistor connected to the ATX 5V output. The
Pinout
operation of the 5V
output is dictated not only by the
DUAL
HIP6503
status of the S3 and S5 pins, but that of the EN5VDL pin as
well. The 3.3V /3.3V and 1.8V outputs are active
(SOIC)
TOP VIEW
DUAL
SB SB
for as long as the ATX 5VSB voltage is applied to the chip.
The 2.5V output is only active during S0 and S1/S2, and
20
1
2
VSEN2
5VSB
CLK
uses the 3V3 pin as input source for its internal pass
element.
19 DRV2
1V8IN
1V8SB
18
3
5V
17
3V3DLSB
3V3DL
VCLK
4
12V
16 SS
5
5VDL
15
14
6
5VDLSB
3V3
7
EN5VDL
13 DLA
8
12
11
9
FAULT/MSEL
GND
S3
S5
10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, 2005. All Rights Reserved
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