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HIP2103FRTAAZ

更新时间： 2024-11-16 12:18:27
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英特矽尔 - INTERSIL 驱动器
页数 文件大小 规格书
21页 504K
描述
60V, 1A/2A Peak, 1/2 Bridge Driver with 4V UVLO

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HIP2103FRTAAZ 数据手册

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60V, 1A/2A Peak, 1/2 Bridge Driver with 4V UVLO  
HIP2103, HIP2104  
The HIP2103 and HIP2104 are half bridge drivers designed for  
applications using DC motors, three-phase brushless DC  
motors, or other similar loads.  
Features  
• 60V maximum bootstrap supply voltage  
• 3.3V and 12V LDOs with dedicated enable pins (HIP2104)  
• 5µA sleep mode quiescent current  
Two inputs (HI and LI) are provided to independently control  
the high side driver (HO) and the low side driver (LO).  
Furthermore, the two inputs can be configured to  
enable/disable the device, thus lowering the number of  
connections to a microcontroller and lowering costs.  
• 4V undervoltage lockout  
• 3.3V or 5V CMOS compatible inputs with hysteresis  
• Integrated bootstrap FET (replaces traditional boot strap diode)  
Applications  
The very low IDD bias current in the Sleep Mode prevents  
battery drain when the device is not in use, thus eliminating  
the need for an external switch to disconnect the driver from  
the battery.  
• Half bridge, full bridge and BLDC motor drives  
(see Figures 21, 22, 23)  
• UPS and inverters  
A fail-safe mechanism is included to improve system reliability  
and to minimize the possibility of catastrophic bridge failures  
due to controller malfunction. Internal logic prevents both  
outputs from turning on simultaneously when HI and LI are  
both high simultaneously. Dead-time is still required on the  
rising edge of the HI (or LI) input when the LI (or HI) input  
transitions low.  
• Class-D amplifiers  
• Any switch mode power circuit requiring a half bridge driver  
Related Literature  
• AN1896 “HIP2103, HIP2104 Evaluation Board User’s Guide”  
• AN1899 “HIP2103, HIP2104 3-phase, Full or Half Bridge  
Motor Drive”  
Integrated pull-down resistors on all of the inputs (LI, HI, VDen  
and VCen) reduces the need for external resistors. An active  
low resistance pull-down on the LO output ensures that the low  
side bridge FET remains off during the Sleep Mode or when  
VDD is below the undervoltage lockout (UVLO) threshold.  
The HIP2104 has a 12V linear regulator and a 3.3V linear  
regulator with separate enable pins. The 12V regulator  
provides internal bias for VDD and the 3.3V regulator provides  
bias for an external microcontroller (and/or other low voltage  
ICs), thus eliminating the need for discrete LDOs or DC/DC  
converters.  
The HIP2103 is available in a 3x3mm, 8 Ld TDFN package and  
the HIP2104 is available in a 4x4mm, 12 Ld DFN package.  
5.5  
5.0  
VBAT  
VBAT  
VBAT  
VDen  
VCen  
VCC  
HB  
4.5  
4.0  
3.5  
HB  
VDD  
VDD  
VDD  
HO  
HS  
LO  
HO  
HS  
LO  
HI  
LI  
HI  
LI  
HIP2104  
HIP2103  
DC  
MOTOR  
µController  
3.0  
2.5  
2.0  
VSS  
VSS  
EPAD  
EPAD  
10  
20  
30  
(VDC)  
40  
50  
V
BAT  
FIGURE 1. TYPICAL FULL BRIDGE APPLICATION  
FIGURE 2. HIP2104 SHUTDOWN CURRENT vs V  
BAT  
November 27, 2013  
FN8276.0  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013. All Rights Reserved  
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.  
All other trademarks mentioned are the property of their respective owners.  
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