HI-1573, HI-1574
PIN DESCRIPTIONS
PIN
(DIP & SOIC)
SYMBOL FUNCTION
DESCRIPTION
1
2
VDDA
BUSA
BUSA
RXENA
GNDA
VDDB
BUSB
BUSB
RXENB
GNDB
RXB
power supply
analog output
analog output
digital input
power supply
power supply
analog output
analog output
digital input
power supply
digital output
digital output
digital input
digital input
digital input
digital output
digital output
digital input
digital input
digital input
+3.3 volt power for transceiver A
MIL-STD-1533 bus driver A, positive signal
MIL-STD-1553 bus driver A, negative signal
Receiver A enable. If low, forces RXA and RXA low (HI-1573) or High (HI-1574)
Ground for transceiver A
3
4
5
6
+3.3 volt power for transceiver B
7
MIL-STD-1533 bus driver B, positive signal
MIL-STD-1553 bus driver B, negative signal
Receiver B enable. If low, forces RXB and RXB low (HI-1573) or High (HI-1574)
Ground for transceiver B
8
9
10
11
12
13
14
15
16
17
18
19
20
Receiver B output, inverted
RXB
Receiver B output, non-inverted
TXINHB
TXB
Transmit inhibit, bus B. If high BUSB, BUSB disabled
Transmitter B digital data input, non-inverted
Transmitter B digital data input, inverted
Receiver A output, inverted
TXB
RXA
RXA
Receiver A output, non-inverted
TXINHA
TXA
Transmit inhibit, bus A. If high BUSA, BUSA disabled
Transmitter A digital data input, non-inverted
Transmitter A digital data input, inverted
TXA
FUNCTIONAL DESCRIPTION
The HI-1573 family of data bus transceivers contains differ- The receiver’s differential input stage drives a filter and
ential voltage source drivers and differential receivers. They threshold comparator that produces CMOS data at the
are intended for applications using a MIL-STD-1553 A/B RXA/B and RXA/B output pins. When the MIL-STD-1553
data bus. The device produces a trapezoidal output wave- bus is idle and RXENA or RXENB are high, RXA/B will be
form during transmission.
logic “0” on HI-1573 and logic “1” on HI-1574.
TRANSMITTER
The receiver outputs are forced to the bus idle state (logic "0”
on HI-1573 or logic “1” on HI-1574) when RXENA or RXENB
Data input to the device’s transmitter section is from the com- is low.
plementary CMOS inputs TXA/B and TXA/B. The transmit-
ter accepts Manchester II bi-phase data and converts it to dif- MIL-STD-1553 BUS INTERFACE
ferential voltages on BUSA/B and BUSA/B. The transceiver
outputs are either direct- or transformer-coupled to the MIL- A direct-coupled interface (see Figure 2) uses a 1:2.5 ratio
STD-1553 data bus. Both coupling methods produce a nomi- isolation transformer and two 55 ohm isolation resistors
nal voltage on the bus of 7.5 volts peak to peak.
between the transformer and the bus. The primary center-
tap of the isolation transformer must be connected to GND.
The transmitter is automatically inhibited and placed in the
high impedance state when both TXA/B and TXA/B are In a transformer-coupled interface (see Figure 2), the
driven with the same logic state. A logic “1” applied to the transceiver is connected to a 1:1.79 isolation transformer
TXINHA/B input will force the transmitter to the high imped- which in turn is connected to a 1:1.4 coupling transformer.
ance state, regardless of the state ofTXA/B and TXA/B.
The transformer-coupled method also requires two coupling
resistors equal to 75% of the bus characteristic impedence
(Zo) between the coupling transformer and the bus.
RECEIVER
The receiver accepts bi-phase differential data from the MIL- Figure 3 and Figure 4 show test circuits for measuring
STD-1553 bus through the same direct- or transformer- electrical characteristics of both direct- and transformer-
coupled interface as the transmitter.
coupled interfaces respectively. (See electrical
characteristics on the following pages).
HOLT INTEGRATED CIRCUITS
2