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HD74LV125ATELL PDF预览

HD74LV125ATELL

更新时间: 2024-11-06 05:10:55
品牌 Logo 应用领域
瑞萨 - RENESAS
页数 文件大小 规格书
10页 80K
描述
Quad. Bus Buffer Gates with 3-state Outputs

HD74LV125ATELL 数据手册

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HD74LV125A  
Quad. Bus Buffer Gates with 3-state Outputs  
REJ03D0315–0300Z  
(Previous ADE-205-245A (Z))  
Rev.3.00  
Jun. 03, 2004  
Description  
The HD74LV125A features independent line drivers with three state outputs. Each output is disabled when the  
associated output enable (OE) input is high. To ensure the high impedance state during power up or power down, OE  
should be connected to VCC through a pull-down resistor; the minimum value of the resistor is determined by the  
current souring capability of the driver. Low-voltage and high-speed operation is suitable for the battery-powered  
products (e.g., notebook computers), and the low-power consumption extends the battery life.  
Features  
VCC = 2.0 V to 5.5 V operation  
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)  
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)  
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)  
Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)  
Output current ±8 mA (@VCC = 3.0 V to 3.6 V), ±16 mA (@VCC = 4.5 V to 5.5 V)  
Ordering Information  
Part Name  
Package Type  
Package Code  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
HD74LV125AFPEL  
HD74LV125ARPEL  
HD74LV125ATELL  
SOP–14 pin(JEITA)  
SOP–14 pin(JEDEC)  
TSSOP–14 pin  
FP–14DAV  
FP–14DNV  
TTP–14DV  
FP  
RP  
T
EL (2,000 pcs/reel)  
EL (2,500 pcs/reel)  
ELL (2,000 pcs/reel)  
Note: Please consult the sales office for the above package availability.  
Function Table  
Inputs  
Output Y  
OE  
L
A
H
L
H
L
L
H
X
Z
Note: H: High level  
L: Low level  
X: Immaterial  
Z: High impedance  
Rev.3.00 Jun. 03, 2004 page 1 of 9  

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