Datasheet > HD74LV05AT

HD74LV05AT

更新时间： 2024-09-16 23:55:27

品牌	Logo	应用领域
其他 - ETC		触发器逻辑集成电路光电二极管栅
页数	文件大小	规格书
11页	364K
描述
LOGIC GATE\|HEX INVERTER\|LV-CMOS\|TSSOP\|14PIN\|PLASTIC

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HD74LV05AT 数据手册

HD74LV74A

Dual D–type Flip Flops with Preset and Clear

ADE-205-244 (Z)

1st Edition

March 1999

Description

The HD74LV74A has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package.

The input data is transferred to the output at the rising edge of clock pulse CLK. Low-voltage and high-speed

operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power con-

sumption extends the battery life.

Features

•

V_CC= 2.0 V to 5.5 V operation

All inputs V_IH(Max.) = 5.5 V (@V_CC= 0 V to 5.5 V)

All outputs V_O(Max.) = 5.5 V (@V_CC= 0 V)

Typical V_OLground bounce < 0.8 V (@V_CC= 3.3 V, Ta = 25°C)

Typical V_OHundershoot > 2.3 V (@V_CC= 3.3 V, Ta = 25°C)

Output current ±6 mA (@V_CC= 3.0 V to 3.6 V), ±12 mA (@V_CC= 4.5 V to 5.5 V)

Function Table

Inputs

Outputs

PRE

CLR

CLK

H*¹

↑

↓

Q₀

Note: H:High level

L:Low level

X:Immaterial

↑:Low to high transition

↓:High to low transition

Q₀:The level of Q immediately before the input conditions shown in the above table are determined.

1.:Q and Q will remain HIGH as long as Preset and Clear are Low, but Q and Q are unpredictable, if

Preset and Clear go HIGH simultaneously.

12 3 4 5 6 7...11

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