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HD74LS390FPEL PDF预览

HD74LS390FPEL

更新时间: 2024-11-26 05:35:15
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瑞萨 - RENESAS 计数器
页数 文件大小 规格书
6页 172K
描述
Dual Decade Counters

HD74LS390FPEL 数据手册

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HD74LS390  
Dual Decade Counters  
REJ03D0485-0400  
Rev.4.00  
May 10, 2006  
This circuit contains eight master-slave flip-flops and additional gating to implement two individual four-bit counters.  
The HD74LS390 incorporates dual divide-by-two and divide-by-five counters, which can be used to implement cycle  
lengths equal to any whole and / or cumulative multiples of 2 and / or 5 up to divide-by-100. When connected as a bi-  
quinary counter, the separate divide-by-two circuit can be used to provide symmetry (a square wave) at the final output  
stage.  
Features  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbre
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-16 pin  
PRDP0016AE-B  
(DP-16FV)  
HD74LS390P  
HD74LS390FPEL  
P
PRSP0016DH-B  
(FP-16DAV)  
SOP-16 pin (JEITA)  
L (2,000 pcs/reel)  
Note: Please consult the sales office for the above package
Pin Arrangement  
7
8
16  
15  
14  
13  
12  
11  
10  
9
1A  
VCC  
1Cle
2A  
2Clear  
CLR  
2Q  
2A  
2Q  
Output  
A
A
1Q  
1Q  
1Q  
B
C
D
2B  
2B  
2QB  
Output
2Q  
2Q  
2Q  
B
C
D
2Q  
C
D
1Q  
Outputs  
2Q  
GND  
(Top view)  
Rev.4.00, May 10, 2006, page 1 of 5  

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