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HD74LS390P-E PDF预览

HD74LS390P-E

更新时间: 2024-11-23 13:08:15
品牌 Logo 应用领域
瑞萨 - RENESAS 计数器
页数 文件大小 规格书
6页 172K
描述
LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDIP16, 6.30 X 19.20 MM, 2.54 MM PITCH, PLASTIC, DIP-16

HD74LS390P-E 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:DIP包装说明:6.30 X 19.20 MM, 2.54 MM PITCH, PLASTIC, DIP-16
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.19
Is Samacsys:N其他特性:ONE FUNCTION HAS 1 BIT
计数方向:UP系列:LS
JESD-30 代码:R-PDIP-T16JESD-609代码:e4
长度:19.2 mm负载/预设输入:YES
逻辑集成电路类型:DECADE COUNTER工作模式:ASYNCHRONOUS
湿度敏感等级:1位数:3
功能数量:2端子数量:16
最高工作温度:75 °C最低工作温度:-20 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):60 ns
认证状态:Not Qualified座面最大高度:5.06 mm
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL EXTENDED
端子面层:NICKEL PALLADIUM GOLD端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:NEGATIVE EDGE
宽度:7.62 mm最小 fmax:25 MHz
Base Number Matches:1

HD74LS390P-E 数据手册

 浏览型号HD74LS390P-E的Datasheet PDF文件第2页浏览型号HD74LS390P-E的Datasheet PDF文件第3页浏览型号HD74LS390P-E的Datasheet PDF文件第4页浏览型号HD74LS390P-E的Datasheet PDF文件第5页浏览型号HD74LS390P-E的Datasheet PDF文件第6页 
HD74LS390  
Dual Decade Counters  
REJ03D0485-0400  
Rev.4.00  
May 10, 2006  
This circuit contains eight master-slave flip-flops and additional gating to implement two individual four-bit counters.  
The HD74LS390 incorporates dual divide-by-two and divide-by-five counters, which can be used to implement cycle  
lengths equal to any whole and / or cumulative multiples of 2 and / or 5 up to divide-by-100. When connected as a bi-  
quinary counter, the separate divide-by-two circuit can be used to provide symmetry (a square wave) at the final output  
stage.  
Features  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbre
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-16 pin  
PRDP0016AE-B  
(DP-16FV)  
HD74LS390P  
HD74LS390FPEL  
P
PRSP0016DH-B  
(FP-16DAV)  
SOP-16 pin (JEITA)  
L (2,000 pcs/reel)  
Note: Please consult the sales office for the above package
Pin Arrangement  
7
8
16  
15  
14  
13  
12  
11  
10  
9
1A  
VCC  
1Cle
2A  
2Clear  
CLR  
2Q  
2A  
2Q  
Output  
A
A
1Q  
1Q  
1Q  
B
C
D
2B  
2B  
2QB  
Output
2Q  
2Q  
2Q  
B
C
D
2Q  
C
D
1Q  
Outputs  
2Q  
GND  
(Top view)  
Rev.4.00, May 10, 2006, page 1 of 5  

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