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HD74LS393RPEL PDF预览

HD74LS393RPEL

更新时间: 2024-11-26 05:35:15
品牌 Logo 应用领域
瑞萨 - RENESAS 计数器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 69K
描述
Dual 4-bit Binary Counters

HD74LS393RPEL 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP16,.25针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.48Is Samacsys:N
计数方向:UP系列:LS
JESD-30 代码:R-PDSO-G14长度:8.65 mm
负载/预设输入:NO逻辑集成电路类型:BINARY COUNTER
最大频率@ Nom-Sup:25000000 Hz最大I(ol):0.008 A
工作模式:ASYNCHRONOUS湿度敏感等级:1
位数:4功能数量:2
端子数量:14最高工作温度:75 °C
最低工作温度:-20 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):26 mA
传播延迟(tpd):60 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Counters
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL EXTENDED
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:NEGATIVE EDGE宽度:3.95 mm
最小 fmax:25 MHzBase Number Matches:1

HD74LS393RPEL 数据手册

 浏览型号HD74LS393RPEL的Datasheet PDF文件第2页浏览型号HD74LS393RPEL的Datasheet PDF文件第3页浏览型号HD74LS393RPEL的Datasheet PDF文件第4页浏览型号HD74LS393RPEL的Datasheet PDF文件第5页浏览型号HD74LS393RPEL的Datasheet PDF文件第6页浏览型号HD74LS393RPEL的Datasheet PDF文件第7页 
HD74LS393  
Dual 4-bit Binary Counters  
REJ03D0486–0200  
Rev.2.00  
Feb.18.2005  
This circuit contains eight master-slave flip-flops and additional gating to implement two individual four-bit counters.  
The HD74LS393 comprises two independent four-bit binary counters each having a clear and a clock input.  
N-bit binary counter can be implemented with each package providing the capability of divide-by-258.  
Features  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
PRDP0014AB-B  
(DP-14AV)  
HD74LS393P  
DILP-14 pin  
P
PRSP0014DF-B  
(FP-14DAV)  
HD74LS393FPEL  
HD74LS393RPEL  
SOP-14 pin (JEITA)  
SOP-14 pin (JEDEC)  
FP  
RP  
EL (2,000 pcs/reel)  
EL (2,500 pcs/reel)  
PRSP0014DE-A  
(FP-14DNV)  
Note: Please consult the sales office for the above package availability.  
Pin Arrangement  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1A  
VCC  
1Clear  
2A  
CLR  
Q
A
B
C
D
1Q  
A
B
2Clear  
CLR  
A
Q
Q
Q
Q
A
1Q  
2Q  
2Q  
2Q  
2Q  
A
B
C
D
A
Outputs  
Q
B
1Q  
C
D
Outputs  
Q
Q
C
D
1Q  
8
GND  
(Top view)  
Rev.2.00, Feb.18.2005, page 1 of 6  

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