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HD74LS42 PDF预览

HD74LS42

更新时间: 2024-11-23 05:35:15
品牌 Logo 应用领域
瑞萨 - RENESAS 解码器
页数 文件大小 规格书
7页 99K
描述
BCD-to-Decimal Decoder

HD74LS42 数据手册

 浏览型号HD74LS42的Datasheet PDF文件第2页浏览型号HD74LS42的Datasheet PDF文件第3页浏览型号HD74LS42的Datasheet PDF文件第4页浏览型号HD74LS42的Datasheet PDF文件第5页浏览型号HD74LS42的Datasheet PDF文件第6页浏览型号HD74LS42的Datasheet PDF文件第7页 
HD74LS42  
BCD-to-Decimal Decoder  
REJ03D0409–0300  
Rev.3.00  
Jul.22.2005  
This monolithic decimal decoder consists of eight inverters and ten four-input NAND gates. The inverters are  
connected in pairs to make BCD input data available for decoding by NAND gates. Full decoding of valid input logic  
ensures that all outputs remain off for all invalid input conditions.  
Features  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
PRDP0016AE-B  
(DP-16FV)  
HD74LS42P  
DILP-16 pin  
P
PRSP0016DH-B  
(FP-16DAV)  
HD74LS42FPEL  
HD74LS42RPEL  
SOP-16 pin (JEITA)  
SOP-16 pin (JEDEC)  
FP  
RP  
EL (2,000 pcs/reel)  
EL (2,500 pcs/reel)  
PRSP0016DG-A  
(FP-16DNV)  
Note: Please consult the sales office for the above package availability.  
Pin Arrangement  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
0Y  
1Y  
VCC  
0
1
2
3
4
5
6
7
8
9
A
B
C
D
A
2Y  
B
Inputs  
Outputs  
3Y  
C
4Y  
D
5Y  
9Y  
6Y  
8Y Outputs  
7Y  
GND  
(Top view)  
Rev.3.00, Jul.22.2005, page 1 of 6  

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