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HD74LS48P-E PDF预览

HD74LS48P-E

更新时间: 2024-11-23 13:08:19
品牌 Logo 应用领域
瑞萨 - RENESAS 驱动器
页数 文件大小 规格书
7页 177K
描述
LS SERIES, SEVEN SEGMENT DECODER/DRIVER, TRUE OUTPUT, PDIP16, 6.30 X 19.20 MM, 2.54 MM PITCH, PLASTIC, DIP-16

HD74LS48P-E 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:16
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.54
Is Samacsys:N系列:LS
输入调节:STANDARDJESD-30 代码:R-PDIP-T16
长度:19.2 mm逻辑集成电路类型:SEVEN SEGMENT DECODER/DRIVER
功能数量:1端子数量:16
最高工作温度:75 °C最低工作温度:-20 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE传播延迟(tpd):100 ns
认证状态:Not Qualified座面最大高度:5.06 mm
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL EXTENDED
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

HD74LS48P-E 数据手册

 浏览型号HD74LS48P-E的Datasheet PDF文件第2页浏览型号HD74LS48P-E的Datasheet PDF文件第3页浏览型号HD74LS48P-E的Datasheet PDF文件第4页浏览型号HD74LS48P-E的Datasheet PDF文件第5页浏览型号HD74LS48P-E的Datasheet PDF文件第6页浏览型号HD74LS48P-E的Datasheet PDF文件第7页 
HD74LS48  
BCD-to-Seven-Segment Decoder / Driver (Internal Pull-up outputs)  
REJ03D0411–0300  
Rev.3.00  
Jul.22.2005  
HD74LS48 features active high outputs for driving lamp buffers. This circuit has full ripple blanking input / output  
controls and a lamp test input. Display patterns for BCD input counts above 9 are unique symbols to authenticate input  
conditions. This circuit incorporates automatic leading and / or trailing-edge zero-blanking control (RBI and RBO).  
Lamp test (LT) of these types may be performed at any time when the BI / RBO node is at a high level. It contains an  
overriding blanking input (BI) which can be used to control the lamp intensity be pulsing or to inhibit the outputs.  
Inputs and outputs are entirely compatible for use with TTL or DTL logic outputs.  
Features  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbre
Taping Abbreviation  
Quantity)  
Part Name  
Package Type  
PRDP0016AE-B  
(DP-16FV)  
HD74LS48P  
DILP-16 pin  
P
Pin Arrangement  
1
2
8
15  
14  
13  
12  
11  
10  
9
B
C
VCC  
Inputs  
f
Lamp  
Tes
a
b
c
d
e
g
a
b
c
d
e
BI/
O  
Outputs  
I  
D
A
G
(Top view)  
Rev.3.00, Jul.22.2005, page 1 of 6  

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