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HD74LS273 PDF预览

HD74LS273

更新时间: 2024-11-12 05:35:15
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瑞萨 - RENESAS 触发器
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7页 98K
描述
Octal D-type Positive-edge-triggered Flip-Flops (with Clear)

HD74LS273 数据手册

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HD74LS273  
Octal D-type Positive-edge-triggered Flip-Flops (with Clear)  
REJ03D0473–0300  
Rev.3.00  
Jul.15.2005  
The HD74LS273, positive-edge-triggered flip-flops utilize LS TTL circuitry to implement D-type flip-flop logic with a  
direct clear input.  
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going  
edge of the clock pulse.  
When the clock input is at either the high or low level, the D input signal has no effect at the output.  
Features  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-20 pin  
PRDP0020AC-B  
(DP-20NEV)  
HD74LS273P  
P
PRSP0020DD-B  
(FP-20DAV)  
HD74LS273FPEL SOP-20 pin (JEITA)  
HD74LS273RPEL SOP-20 pin (JEDEC)  
FP  
RP  
EL (2,000 pcs/reel)  
EL (1,000 pcs/reel)  
PRSP0020DC-A  
(FP-20DBV)  
Note: Please consult the sales office for the above package availability.  
Pin Arrangement  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
Clear  
1Q  
VCC  
Q
D
Q
D
8Q  
8D  
Clear  
CK  
Clear  
CK  
3
1D  
4
2D  
D
Q
CK  
Clear  
CK  
Clear  
D
Q
7D  
5
2Q  
7Q  
6Q  
6D  
6
3Q  
Q
D
Q
D
Clear  
CK  
Clear  
CK  
7
3D  
8
4D  
5D  
D
Q
CK  
Clear  
CK  
Clear  
D
Q
9
4Q  
5Q  
Clock  
10  
GND  
(Top view)  
Rev.3.00, Jul.15.2005, page 1 of 6  

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