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HD74HC74FP PDF预览

HD74HC74FP

更新时间: 2024-02-13 21:22:30
品牌 Logo 应用领域
日立 - HITACHI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
9页 55K
描述
D Flip-Flop, HC/UH Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14, FP-14DA

HD74HC74FP 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:SOIC包装说明:SOP, SOP14,.3
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.1
系列:HC/UHJESD-30 代码:R-PDSO-G14
长度:10.06 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:20000000 Hz
最大I(ol):0.004 A湿度敏感等级:1
位数:1功能数量:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:2/6 V
传播延迟(tpd):200 ns认证状态:Not Qualified
座面最大高度:2.2 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:5.5 mmBase Number Matches:1

HD74HC74FP 数据手册

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HD74HC74  
Dual D-type Flip-Flops (with Preset and Clear)  
Description  
The flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level  
present at thte data input is transferred to the output during the positive going transition to the clock pulse.  
Preset and clear are independent of the clock and accomplished by a low level at the appropriate input.  
Features  
High Speed Operation: tpd (Clock to Q or Q) = 14 ns typ (CL = 50 pF)  
High Output Current: Fanout of 10 LSTTL Loads  
Wide Operating Voltage: VCC = 2 to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C)  
Function Table  
Inputs  
Outputs  
Preset  
Clear  
Clock  
Data  
X
Q
Q
L
H
L
X
X
X
H
L
H
L
X
L
H*1  
H
H*1  
L
X
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
L
X
no change  
no change  
no change  
no change  
no change  
no change  
H
X
X
Note: 1. Q and Q will remain HIGH as long as Preset and Clear are Low, but Q and Q are unpredictable,  
if Preset and Clear go HIGH simultaneously.  

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