5秒后页面跳转
HD74ACT107P PDF预览

HD74ACT107P

更新时间: 2024-11-13 19:52:15
品牌 Logo 应用领域
日立 - HITACHI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
10页 56K
描述
ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14, DP-14

HD74ACT107P 数据手册

 浏览型号HD74ACT107P的Datasheet PDF文件第2页浏览型号HD74ACT107P的Datasheet PDF文件第3页浏览型号HD74ACT107P的Datasheet PDF文件第4页浏览型号HD74ACT107P的Datasheet PDF文件第5页浏览型号HD74ACT107P的Datasheet PDF文件第6页浏览型号HD74ACT107P的Datasheet PDF文件第7页 
HD74AC107/HD74ACT107  
Dual JK Flip-Flop (with Separate Clear and Clock)  
Description  
The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop.  
Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the  
coupling transistors which connect the master and slave sections. The sequence of operation is as follows:  
1) isolate slave from master; 2) enter information from J and K inputs to master; 3) disable J and K inputs;  
4) transfer information from master to slave.  
Features  
Outputs Source/Sink 24 mA  
HD74ACT107 has TTL-Compatible Inputs  
Pin Arrangement  
J1  
Q1  
Q1  
K1  
Q2  
Q2  
1
2
3
4
5
6
14 VCC  
13 CD1  
12 CP1  
11 K2  
10 CD2  
9
8
CP2  
GND 7  
J2  
(Top view)  

与HD74ACT107P相关器件

型号 品牌 获取价格 描述 数据表
HD74ACT107RP ETC

获取价格

FLIP-FLOP|DUAL|J/K TYPE|ACT-CMOS|SOP|14PIN|PLASTIC
HD74ACT107RPEL RENESAS

获取价格

ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, SOP-
HD74ACT107RP-EL HITACHI

获取价格

暂无描述
HD74ACT107RPVEL RENESAS

获取价格

ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, LEAD
HD74ACT107T RENESAS

获取价格

暂无描述
HD74ACT107T HITACHI

获取价格

J-K Flip-Flop, ACT Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, C
HD74ACT107T-EL HITACHI

获取价格

暂无描述
HD74ACT109FP ETC

获取价格

J-K-Type Flip-Flop
HD74ACT109P ETC

获取价格

J-K-Type Flip-Flop
HD74ACT112 HITACHI

获取价格

Dual JK Negative Edge-Triggered Flip-Flop