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HD74ACT107T PDF预览

HD74ACT107T

更新时间: 2024-11-13 13:08:15
品牌 Logo 应用领域
瑞萨 - RENESAS 触发器时钟
页数 文件大小 规格书
7页 209K
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HD74ACT107T 数据手册

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HD74AC107/HD74ACT107  
Dual JK Flip-Flop (with Separate Clear and Clock)  
REJ03D02430200Z  
(Previous ADE-205-363 (Z))  
Rev.2.00  
Jul.16.2004  
Description  
The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop. Inputs to the  
master section are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors  
which connect the master and slave sections. The sequence of operation is as follows: 1) isolate slave from master; 2)  
enter information from J and K inputs to master; 3) disable J and K inputs; 4) transfer information from master to slave.  
Features  
Outputs Source/Sink 24 mA  
HD74ACT107 has TTL-Compatible Inputs  
Ordering Information: Ex. HD74AC107  
Part Name  
Package Type  
Package Code Pabbreviation (Quantity)  
HD74AC107FPEL SOP-14 pin (JEITA) FP-14DAV  
HD74AC107RPEL SOP-14 pin (JEDEC) FP-14DNV  
000 pcs/reel)  
(2,500 pcs/reel)  
Notes: 1. Please consult the sales office for the abov
2. The packages with lead-free pins are disal products by adding V at the end of  
the package code.  
Pin Arrangement  
Q2  
Q2  
4
5
6
14 VCC  
13 CD1  
12 CP1  
11 K2  
10 CD2  
9
8
CP2  
GND 7  
J2  
(Top view)  
Rev.2.00, Jul.16.2004, page 1 of 6  

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