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HCTS4002K/SAMPLE

更新时间： 2024-11-03 15:33:51
品牌 Logo 应用领域
瑞萨 - RENESAS 输入元件逻辑集成电路
页数 文件大小 规格书
8页 174K
描述
HCT SERIES, DUAL 4-INPUT NOR GATE, CDFP14, CERAMIC, DFP-14

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HCTS4002K/SAMPLE 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：DFP,针数：14
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.66系列：HCT
JESD-30 代码：R-CDFP-F14长度：9.525 mm
逻辑集成电路类型：NOR GATE功能数量：2
输入次数：4端子数量：14
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：DFP
封装形状：RECTANGULAR封装形式：FLATPACK
传播延迟（tpd）：22 ns认证状态：Not Qualified
座面最大高度：2.92 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
端子形式：FLAT端子节距：1.27 mm
端子位置：DUAL宽度：6.73 mm
Base Number Matches：1

HCTS4002K/SAMPLE 数据手册

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TM  
HCTS4002MS  
Radiation Hardened  
Dual 4-Input NOR Gate  
August 1995  
Features  
Pinouts  
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL  
PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T14  
TOP VIEW  
• 3 Micron Radiation Hardened CMOS SOS  
• Total Dose 200K RAD (Si)  
2
• SEP Effective LET No Upsets: >100 MEV-cm /mg  
Y1  
A1  
1
2
3
4
5
6
7
14 VCC  
13 Y2  
12 D2  
11 C2  
10 B2  
-9  
• Single Event Upset (SEU) Immunity < 2 x 10 Errors/Bit-Day  
(Typ)  
B1  
12  
• Dose Rate Survivability: >1 x 10 RAD (Si)/s  
C1  
10  
• Dose Rate Upset >10 RAD (Si)/s 20ns Pulse  
D1  
• Latch-Up Free Under Any Conditions  
NC  
GND  
9
8
A2  
o
o
• Military Temperature Range: -55 C to +125 C  
• Significant Power Reduction Compared to LSTTL ICs  
• DC Operating Voltage Range: 4.5V to 5.5V  
NC  
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE  
(FLATPACK) MIL-STD-1835 CDFP3-F14  
TOP VIEW  
• LSTTL Input Compatibility  
- VIL = 0.8V Max  
- VIH = VCC/2 Min  
Y1  
A1  
1
2
3
4
5
6
7
14  
13  
VCC  
Y2  
• Input Current Levels Ii ≤ 5µA at VOL, VOH  
12  
11  
10  
B1  
D2  
Description  
C1  
C2  
The Intersil HCTS4002MS is a Radiation Hardened Dual 4-Input  
NOR Gate. A high on any input forces the output to a low state.  
D1  
B2  
NC  
GND  
A2  
9
8
The HCTS4002MS utilizes advanced CMOS/SOS technology to  
achieve high-speed operation. This device is a member of  
radiation hardened, high-speed, CMOS/SOS Logic Family.  
NC  
The HCTS4002MS is supplied in a 14 lead Ceramic flatpack (K  
suffix) or a SBDIP Package (D suffix).  
Functional Diagram  
An  
Bn  
Ordering Information  
Yn  
Cn  
Dn  
PART  
NUMBER  
TEMPERATURE SCREENING  
RANGE LEVEL  
PACKAGE  
HCTS4002DMSR -55oC to +125oC Intersil Class  
S Equivalent  
14 Lead SBDIP  
TRUTH TABLE  
INPUTS  
HCTS4002KMSR -55oC to +125oC Intersil Class  
S Equivalent  
14 Lead  
Ceramic  
Flatpack  
OUTPUTS  
An  
L
Bn  
Cn  
L
Dn  
L
Yn  
H
L
L
X
H
X
X
HCTS4002D/  
Sample  
+25oC  
+25oC  
Sample  
Sample  
14 Lead SBDIP  
H
X
X
X
X
X
L
HCTS4002K/  
Sample  
14 Lead  
Ceramic  
Flatpack  
X
H
X
X
L
X
H
L
HCTS4002HMSR  
+25oC  
Die  
Die  
NOTE: L = Logic Level Low, H = Logic level High,  
X = Don’t Care  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.  
Spec Number 518632  
FN3075.1  
Copyright © Intersil Americas Inc. 2002. All Rights Reserved  
718  
12345678

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HCTS540K/SAMPLE RENESAS

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HCTS540KMSH RENESAS

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