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HCPL-7710#500 PDF预览

HCPL-7710#500

更新时间: 2024-11-04 20:24:43
品牌 Logo 应用领域
安捷伦 - AGILENT 输出元件光电
页数 文件大小 规格书
17页 433K
描述
1 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 12.5 Mbps, 0.300 INCH, SURFACE MOUNT, DIP-8

HCPL-7710#500 技术参数

生命周期:Transferred包装说明:0.300 INCH, SURFACE MOUNT, DIP-8
Reach Compliance Code:unknown风险等级:5.2
Is Samacsys:N其他特性:UL RECOGNIZED
配置:SINGLE标称数据速率:12.5 MBps
最大正向电流:0.01 A最大绝缘电压:3750 V
元件数量:1最大通态电流:0.01 A
最高工作温度:100 °C最低工作温度:-40 °C
光电设备类型:LOGIC IC OUTPUT OPTOCOUPLER最小供电电压:4.5 V
Base Number Matches:1

HCPL-7710#500 数据手册

 浏览型号HCPL-7710#500的Datasheet PDF文件第2页浏览型号HCPL-7710#500的Datasheet PDF文件第3页浏览型号HCPL-7710#500的Datasheet PDF文件第4页浏览型号HCPL-7710#500的Datasheet PDF文件第5页浏览型号HCPL-7710#500的Datasheet PDF文件第6页浏览型号HCPL-7710#500的Datasheet PDF文件第7页 
Agilent HCPL-7710, HCPL-0710  
40 ns Propagation Delay,  
CMOS Optocoupler  
Data Sheet  
Features  
+5 V CMOS compatibility  
• 8 ns maximum pulse width  
distortion  
• 20 ns maximum prop. delay skew  
High speed: 12 Mbd  
• 40 ns maximum prop. delay  
Description  
Basic building blocks of the  
HCPL-x710 are a CMOS LED  
driver IC, a high speed LED and a  
CMOS detector IC. A CMOS logic  
input signal controls the LED  
driver IC which supplies current  
to the LED. The detector IC  
incorporates an integrated  
photodiode, a high-speed  
• 10 kV/ µs minimum common mode  
rejection  
Available in either an 8-pin DIP or  
SO-8 package style respectively,  
the HCPL-7710 or HCPL-0710  
optocouplers utilize the latest  
CMOS IC technology to achieve  
outstanding performance with  
very low power consumption. The  
HCPL-x710 require only two  
bypass capacitors for complete  
CMOS compatibility.  
• -40°C to 100°C temperature range  
• Safety and regulatory approvals  
UL Recognized  
3750 V rms for 1 min. per  
UL 1577  
CSA Component Acceptance  
Notice # 5  
transimpedance amplifier, and a  
voltage comparator with an  
output driver.  
IEC/ EN/ DIN EN 60747-5-2  
VIORM = 630 Vpeak for  
HCPL-7710 Option 060  
Functional Diagram  
VIORM = 560 Vpeak for  
HCPL-0710 Option 060  
TRUTH TABLE  
(POSITIVE LOGIC)  
**V  
1
2
8
7
V
**  
DD2  
DD1  
Applications  
V , INPUT  
I
LED1  
V
, OUTPUT  
O
H
L
OFF  
ON  
H
L
Digital fieldbus isolation:  
DeviceNet, SDS, Profibus  
V
I
NC*  
I
O
AC plasma display panel level  
shifting  
3
4
6
5
*
V
O
LED1  
• Multiplexed data transmission  
Computer peripheral interface  
• Microprocessor system interface  
GND  
GND  
2
1
SHIELD  
* Pin 3 is the anode of the internal LED and must be left unconnected for guaranteed data sheet  
performance. Pin 7 is not connected internally.  
** A 0.1 µF bypass capacitor must be connected between pins 1 and 4, and 5 and 8.  
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this  
component to prevent damage and/or degradation which may be induced by ESD.  

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