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HCF4096BC1 PDF预览

HCF4096BC1

更新时间: 2024-11-03 22:20:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器锁存器逻辑集成电路输入元件
页数 文件大小 规格书
13页 297K
描述
GATE J-K MASTER-SLAVE FLIP-FLOPS

HCF4096BC1 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:QLCC
包装说明:PLASTIC, LCC-20针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.75Is Samacsys:N
其他特性:2 NON-INVERTED & 1 INVERTED J/K INPUTS ANDED系列:4000/14000/40000
JESD-30 代码:S-PQCC-J20JESD-609代码:e3
长度:8.965 mm负载电容(CL):50 pF
逻辑集成电路类型:J-K FLIP-FLOP最大频率@ Nom-Sup:3500000 Hz
位数:2功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC20,.4SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:3/15 V传播延迟(tpd):500 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:FF/Latches最大供电电压 (Vsup):15 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:8.965 mm
最小 fmax:3.5 MHzBase Number Matches:1

HCF4096BC1 数据手册

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HCC/HCF4095B  
HCC/HCF4096B  
GATE J-K MASTER-SLAVE FLIP-FLOPS  
.
16 MHz TOGGLE RATE (typ.) AT  
VDD - VSS = 10V  
GATED INPUTS  
QUIESCENT CURRENT SPECIFIED TO 20v  
FOR HCC DEVICE  
5V, 10V AND 15V PARAMETRIC RATINGS  
INPUT CURRENTOF 100nA AT18VAND 25oC  
FOR HCC DEVICE  
100% TESTED FOR QUIESCENT CURRENT  
MEETS ALLREQUIREMENTS OF JEDECTEN-  
TATIVE STANDARD No 13 A, ”STANDARD  
SPECIFICATIONS FOR DESCRIPTION OF B  
SERIES CMOS DEVICES”  
inputs is transferred to the Q and Q outputs on the  
positive edge of the clock pulse. SET and RESET  
inputs (active high) are provided for asynchronous  
.
.
operation.  
.
.
.
.
EY  
F
(Plastic Package)  
(Ceramic Package)  
DESCRIPTION  
The HCC4095B/4096B (extended temperature  
range) and HCF4095B/4096B (intermediate tem-  
perature range) are monolithic integrated circuits,  
available in 14 lead dual in-line plastic or ceramic  
package and plastic micropackage.  
M1  
C1  
(Micro Package)  
(Chip Carrier)  
The HCC/HCF4095B and HCC/HCF4096B are J-K  
Master-Slave Flip-Flops featuring separate AND  
gatingof multiple J and Kinputs. The gated J-K input  
control transfer of information into the master sec-  
tion during clocked operation. Information onthe J-K  
ORDER CODES :  
HCC40XXBF  
HCF40XXBEY  
HCF40XXBM1  
HCF40XXBC1  
PIN CONNECTIONS  
4095B  
4096B  
September 1988  
1/13  

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