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HCF4096BEY PDF预览

HCF4096BEY

更新时间: 2024-11-19 22:57:03
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器
页数 文件大小 规格书
13页 297K
描述
GATE J-K MASTER-SLAVE FLIP-FLOPS

HCF4096BEY 数据手册

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HCC/HCF4095B  
HCC/HCF4096B  
GATE J-K MASTER-SLAVE FLIP-FLOPS  
.
16 MHz TOGGLE RATE (typ.) AT  
VDD - VSS = 10V  
GATED INPUTS  
QUIESCENT CURRENT SPECIFIED TO 20v  
FOR HCC DEVICE  
5V, 10V AND 15V PARAMETRIC RATINGS  
INPUT CURRENTOF 100nA AT18VAND 25oC  
FOR HCC DEVICE  
100% TESTED FOR QUIESCENT CURRENT  
MEETS ALLREQUIREMENTS OF JEDECTEN-  
TATIVE STANDARD No 13 A, ”STANDARD  
SPECIFICATIONS FOR DESCRIPTION OF B  
SERIES CMOS DEVICES”  
inputs is transferred to the Q and Q outputs on the  
positive edge of the clock pulse. SET and RESET  
inputs (active high) are provided for asynchronous  
.
.
operation.  
.
.
.
.
EY  
F
(Plastic Package)  
(Ceramic Package)  
DESCRIPTION  
The HCC4095B/4096B (extended temperature  
range) and HCF4095B/4096B (intermediate tem-  
perature range) are monolithic integrated circuits,  
available in 14 lead dual in-line plastic or ceramic  
package and plastic micropackage.  
M1  
C1  
(Micro Package)  
(Chip Carrier)  
The HCC/HCF4095B and HCC/HCF4096B are J-K  
Master-Slave Flip-Flops featuring separate AND  
gatingof multiple J and Kinputs. The gated J-K input  
control transfer of information into the master sec-  
tion during clocked operation. Information onthe J-K  
ORDER CODES :  
HCC40XXBF  
HCF40XXBEY  
HCF40XXBM1  
HCF40XXBC1  
PIN CONNECTIONS  
4095B  
4096B  
September 1988  
1/13  

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