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HCF40193 PDF预览

HCF40193

更新时间: 2024-11-14 12:19:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 计数器时钟
页数 文件大小 规格书
12页 900K
描述
PRESETTABLE UP/DOWN COUNTERS (DUAL CLOCK WITH RESET) BINARY TYPE

HCF40193 数据手册

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HCF40193B  
PRESETTABLE UP/DOWN COUNTERS  
(DUAL CLOCK WITH RESET) BINARY TYPE  
INDIVIDUAL CLOCK LINES FOR COUNTING  
UP OR COUNTING DOWN  
SYNCHRONOUS HIGH-SPEED CARRY AND  
BORROW PROPAGATION DELAYS FOR  
CASCADING  
ASYNCHRONOUS RESET AND PRESET  
CAPABILITY  
DIP  
SOP  
MEDIUM-SPEED OPERATION - f = 8MHz  
CL  
(typ.) AT 10 V  
STANDARDIZED SYMMETRICAL OUTPUT  
CHARACTERISTICS  
QUIESCENT CURRENT SPECIF. UP TO 20V  
5V, 10V AND 15V PARAMETRIC RATINGS  
INPUT LEAKAGE CURRENT  
ORDER CODES  
PACKAGE  
TUBE  
T & R  
DIP  
HCF40193BEY  
HCF40193BM1  
SOP  
HCF40193M013TR  
I = 100nA (MAX) AT V = 18V T = 25°C  
I
DD  
A
and BORROW outputs for multiple-stage counting  
schemes are provided. The counter is cleared so  
that all outputs are in a low state by a high on the  
100% TESTED FOR QUIESCENT CURRENT  
MEETS ALL REQUIREMENTS OF JEDEC  
JESD13B "STANDARD SPECIFICATIONS  
FOR DESCRIPTION OF B SERIES CMOS  
DEVICES"  
RESET line.  
A
RESET is accomplished  
asynchronously with the clock. Each output is  
individually programmable asynchronously with  
the clock to the level on the corresponding jam  
input when the PRESET ENABLE control is low.  
The counter counts up one count on the positive  
clock edge of the CLOCK UP signal provided the  
CLOCK DOWN line is high. The counter counts  
down one count on the positive clock edge of the  
CLOCK DOWN signal provided the CLOCK UP  
line is high. The CARRY and BORROW signals  
are high when the counter counts up or down. The  
CARRY signal goes low one-half clock cycle after  
the counter reaches its maximum count in the  
count-up mode. The BORROW signal goes low  
DESCRIPTION  
HCF40193B is a monolithic integrated circuit  
fabricated in Metal Oxide Semiconductor  
technology available in DIP and SOP packages.  
HCF40193B Presettable Binary Up/Down Counter  
consists of 4 synchronously clocked, GATED "D"  
type flip-flops connected as a counter. The inputs  
consist of four individual jam lines, a PRESET  
ENABLE control, individual CLOCK UP and  
CLOCK DOWN signals and a master RESET.  
Four buffered Q signal outputs as well as CARRY  
PIN CONNECTION  
September 2002  
1/12  

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