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HCF40208BE PDF预览

HCF40208BE

更新时间: 2024-11-14 12:59:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
13页 291K
描述
IC,REGISTER FILE,CMOS,DIP,24PIN,PLASTIC

HCF40208BE 技术参数

是否Rohs认证:不符合生命周期:Obsolete
Reach Compliance Code:not_compliant风险等级:5.92
Is Samacsys:NJESD-30 代码:R-PDIP-T24
JESD-609代码:e0端子数量:24
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP24,.6封装形状:RECTANGULAR
封装形式:IN-LINE认证状态:Not Qualified
子类别:Other Memory ICs表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
Base Number Matches:1

HCF40208BE 数据手册

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HCC/HCF40208B  
4 x 4 MULTIPORT REGISTER  
.
.
.
FOUR 4-BIT REGISTERS  
ONE INPUT AND TWO OUTPUT BUSES  
UNLIMITED EXPANSION IN BIT AND WORD  
DIRECTIONS  
DATA LINES HAVE LATCHED INPUTS  
3-STATE OUTPUTS  
SEPARATE CONTROL OF EACH BUS,  
ALLOWING SIMULTANEOUS INDEPENDENT  
READING OF ANY OF FOUR REGISTERS ON  
BUS A AND BUS B AND INDEPENDENT WRIT-  
ING INTO ANY OF THE FOUR REGISTERS  
40108B IS PIN-COMPATIBLE WITH INDUS-  
TRY TYPE MC14580  
STANDARDIZED, SYMMETRICAL OUTPUT  
CHARACTERISTICS  
QUIESCENT CURRENT SPECIFIED AT 20V  
FOR HCC DEVICE  
5V, 10V, AND 15V PARAMETRIC RATINGS  
INPUT CURRENT OF 100nA AT 18V AND 25°C  
FOR HCC DEVICE  
100% TESTED FOR QUIESCENT CURRENT  
MEETS ALLREQUIREMENTS OF JEDECTEN-  
TATIVESTANDARDN°13A, ”STANDARD SPE-  
CIFICATIONS FOR DESCRIPTION OF ”B”  
SERIES CMOS DEVICES”  
.
.
.
BEY  
BF  
(Plastic Package)  
(Ceramic Frit Seal Package)  
.
.
.
BM1  
(Micro Package)  
ORDER CODES :  
HCC40208BF HCF40208BEY  
HCF40208BM1  
.
.
.
.
PIN CONNECTIONS  
DESCRIPTION  
The HCC40208B (extended temperature range) and  
HCF40208B (intermediate temperature range) are  
monolithic integrated circuits, available in 24-lead dual  
in-line plastic or ceramic package and plastic micro  
package. The HCC/HCF40208B is a 4 x 4 multiport  
register containing four 4-bit registers, write address  
decoder, two separate read address decoders, and  
two 3-state output buses. When the ENABLE input is  
low, the corresponding output bus is switched, inde-  
pendently of theclock to a high-impedance state. The  
high-impedance third state provides the outputs with  
the capability of being connected to the bus lines in a  
bus-organized system without the need for interface or  
pull-up components. When the WRITE ENABLE input  
is high, all data input lines are latched on the positive  
transition of the CLOCKand the data is entered into the  
wordselected bythewriteaddress lines. When WRITE  
ENABLE is low, the CLOCK is inhibited and no new  
data is entered. In either case, the contents of any word  
may be accessed via the read address lines inde-  
pendent of the state of the CLOCK input.  
June 1989  
1/13  

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