Datasheet > HCF401XXBEY

HCF401XXBEY

更新时间： 2024-11-13 22:10:43

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		计数器
页数	文件大小	规格书
13页	272K
描述
8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

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中文翻译

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数据手册

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HCF401XXBEY 数据手册

HCC/HCF40102B

HCC/HCF40103B

8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

40102B 2-DECADE BCD TYPE

40103B 8-BIT BINARY TYPE

SYNCHRONOUS

PRESET

MEDIUM-SPEED OPERATION : f_CL= 3.6MHz

(TYP.) @ V_DD= 10V

CASCADABLE

QUIESCENT CURRENT SPECIFIED TO 20V

FOR HCC DEVICE

5V, 10V AND 15V PARAMETRIC RATINGS

INPUT CURRENT OF100 nA AT 18V AND 25°C

FOR HCC DEVICE

100% TESTED FOR QUIESCENT CURRENT

MEETS ALLREQUIREMENTS OF JEDECTEN-

TATIVE STANDARD N^o. 13 A, ”STANDARD

SPECIFICATIONS FOR DESCRIPTION OF ”B”

SERIES CMOS DEVICES”

ASYNCHRONOUS

(Plastic Package)

(Ceramic Package)

(Chip Carrier)

ORDER CODES :

HCC401XXBF

HCF401XXBEY

HCF401XXBC1

DESCRIPTION

The HCC40102B, HCC40103B, (extended tempera-

ture range) and the HCF40102B, HCF40103B (inter-

mediate temperature range) are monolithic integrated

circuits, available in 16-lead dual in-line plastic or ce-

ramic package. The HCC/HCF40102B, and

HCC/HCF40103B consist of an 8-stagesynchronous

down counterwith asingle output whichisactivewhen

the internal count is zero. The HCC/HCF40102B is

configured as two cascaded 4-bit BCD counters, and

the HCC/HCF40103B contains a single 8-bit binary

counter. Each type has control inputsfor enabling or

disabling the clock, for clearing the counter to its

maximum count, and for presetting the counter

either synchronously or asynchronously. All control

inputs and the CARRY-OUT/ZERO-DETECT out-

put are active-low logic. In normal operation, the

counter is decremented by one count on each posi-

tive transition of the CLOCK. Counting is inhibited

when the CARRY-IN/COUNTER ENABLE (CI/CE)

input is high. The CARRY-OUT/ZERO-DETEC

(CO/ZD) output goes low when the count reaches

zero if the CI/CE input is low, and remains low for

one full clock period. When the SYNCHRONOUS

PRESET-ENABLE (SPE) input is low, data at the

JAM input is clocked into the counter on the next

positive clock transitionregardless of the state of the

CI/CE input. When the ASYNCHRONOUS

PRESET-ENABLE (APE) input is low, data at the

PIN CONNECTIONS

June 1989

1/13

12 3 4 5 6 7...13

中文翻译

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