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HCF40192B PDF预览

HCF40192B

更新时间: 2024-11-13 22:56:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 计数器时钟
页数 文件大小 规格书
15页 316K
描述
PRESETTABLE UP/DOWN COUNTERS (DUAL CLOCK WITH RESET) 40192B BCD TYPE 40193B BINARY TYPE

HCF40192B 数据手册

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HCC/HCF40192B  
HCC/HCF40193B  
PRESETTABLE UP/DOWN COUNTERS (DUAL CLOCK  
WITH RESET) 40192B – BCD TYPE 40193B – BINARY TYPE  
.
.
INDIVIDUAL CLOCK LINES FOR COUNTING  
UP OR COUNTING DOWN  
SYNCHRONOUS HIGH-SPEED CARRY AND  
BORROWPROPAGATION DELAYS FOR CAS-  
CADING  
ASYNCHRONOUS RESET AND PRESET CA-  
PABILITY  
MEDIUM-SPEED OPERATION - fCL = 8MHz  
(typ.) @ 10V  
STANDARDIZED SYMMETRICAL OUTPUT  
CHARACTERISTICS  
5V, 10V, AND 15V PARAMETRIC RATINGS  
INPUT CURRENT OF 100nA AT 18V AND 25°C  
FOR HCC DEVICE  
100% TESTED FOR QUIESCENT CURRENT  
MEETS ALLREQUIREMENTS OF JEDECTEN-  
TATIVESTANDARDN°13A, ”STANDARD SPE-  
CIFICATIONS FOR DESCRIPTION OF ”B”  
SERIES CMOS DEVICES”  
.
.
.
EY  
F
(Plastic Package)  
(Ceramic Frit Seal Package)  
.
.
M1  
C1  
(Chip Carrier)  
(Plastic Chip Carrier)  
.
.
ORDER CODES :  
HCC401XXBF  
HCF401XXBEY  
HCF401XXBM1  
HCF401XXBC1  
PIN CONNECTIONS  
DESCRIPTION  
The HCC40192B, HCC40193B, (extended tem-  
perature range) and the HCF40192B, HCF40193B  
(intermediate temperature range) are monolithic in-  
tegrated circuits, available in 16-lead dual in-line  
plastic or ceramic package and platic micro pack-  
age. The HCC/HCF40192B Presettable BCD  
Up/Down Counter and the HCC/HCF40193B Pres-  
ettable Binary Up/Down Counter each consist of 4  
synchronously clocked, gated ”D” type flip-flops  
connected as a counter. The inputs consist of 4 in-  
dividual jam lines, a PRESET ENABLE control, in-  
dividual CLOCK UP and CLOCK DOWN signals  
and a master RESET. Four buffered Q signal out-  
puts as well as CARRY and BORROW outputs for  
multiple-stage counting schemes are provided. The  
counter is cleared so that all outputs are in a low  
state by a high on the RESET line. A RESET is ac-  
complished asynchronously with the clock. Each  
output is individually programmable asynchron-  
ouslywith theclock tothelevel on the corresponding  
jam input when thePRESET ENABLE control is low.  
The counter counts up one count on the positive  
clock edge of the CLOCK UP signal provided the  
CLOCK DOWN line is high. The counter counts  
down one count on the positive clock edge of the  
CLOCK DOWN signal provided the CLOCK UP line  
June 1989  
1/15  

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暂无描述
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