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HCF4018M013TR PDF预览

HCF4018M013TR

更新时间: 2024-11-14 04:56:47
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 计数器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
11页 443K
描述
PRESETTABLE DIVIDE-BY-N COUNTER

HCF4018M013TR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.54
Is Samacsys:N计数方向:UP
系列:4000/14000/40000JESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:9.9 mm
负载电容(CL):50 pF负载/预设输入:YES
逻辑集成电路类型:RING COUNTER最大频率@ Nom-Sup:3000000 Hz
工作模式:SYNCHRONOUS湿度敏感等级:3
位数:5功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5/15 V传播延迟(tpd):400 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Counters最大供电电压 (Vsup):20 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:3.9 mm
最小 fmax:8.5 MHzBase Number Matches:1

HCF4018M013TR 数据手册

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HCF4018B  
PRESETTABLE DIVIDE-BY-N COUNTER  
MEDIUM SPEED OPERATION 10 MHz (Typ.)  
at V - V = 10V  
DD  
SS  
FULLY STATIC OPERATION  
STANDARDIZED SYMMETRICAL OUTPUT  
CHARACTERISTICS  
QUIESCENT CURRENT SPECIFIED UP TO  
20V  
DIP  
SOP  
5V, 10V AND 15V PARAMETRIC RATINGS  
INPUT LEAKAGE CURRENT  
I = 100nA (MAX) AT V = 18V T = 25°C  
ORDER CODES  
PACKAGE  
I
DD  
A
100% TESTED FOR QUIESCENT CURRENT  
MEETS ALL REQUIREMENTS OF JEDEC  
JESD13B " STANDARD SPECIFICATIONS  
FOR DESCRIPTION OF B SERIES CMOS  
DEVICES"  
TUBE  
T & R  
DIP  
HCF4018BEY  
HCF4018BM1  
SOP  
HCF4018M013TR  
DESCRIPTION  
package to properly gate the feedback connection  
to the DATA input. Divide-by-functions greater  
than 10 can be achieved by use of multiple  
HCF4018B units. The counter is advanced one  
count at the positive clock signalstransition.  
Schmitt trigger action on the clock line permits  
unlimited clock rise and fall times. A high RESET  
signal clears the counter to an all-zero condition. A  
The HCF4018B is a monolithic integrated circuit  
fabricated in Metal Oxide Semiconductor  
technology available in DIP and SOP packages.  
The HCF4018B consist of 5 Johnson counter  
stages, buffered Q outputs from each stage, and  
counter preset control gating. CLOCK, RESET,  
DATA, PRESET ENABLE, and 5 individual JAM  
inputs are provided. Divide by 10, 8, 6, 4 or 2  
counter configuration can be implemented by  
feeding the Q5, Q4, Q3, Q2, Q1 signals,  
respectively, back to the data input.  
high  
PRESENT-ENABLE  
signal  
allows  
information on the JAM inputs to preset the  
counter.  
Anti-lock gating is provided to assure the proper  
counting sequence.  
Divide-by-9, 7, 5, or 3 counter configurations can  
be implemented by the use of a HCF4011B gate  
PIN CONNECTION  
September 2001  
1/11  

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