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HCF4018BC1 PDF预览

HCF4018BC1

更新时间: 2024-09-25 22:24:23
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 计数器触发器逻辑集成电路输出元件输入元件
页数 文件大小 规格书
12页 275K
描述
PRESETTABLE DIVIDE-BY-N COUNTER

HCF4018BC1 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QLCC包装说明:PLASTIC, LCC-20
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.83
Is Samacsys:N其他特性:JOHNSON COUNTER, PROGRAMMABLE WITH EXT CONNECTIONS; SCHMITT TRIGGER ON CLOCK INPUT; INVERTED OUTPUTS
计数方向:UP系列:4000/14000/40000
JESD-30 代码:S-PQCC-J20JESD-609代码:e3
长度:8.965 mm负载电容(CL):50 pF
负载/预设输入:YES逻辑集成电路类型:RING COUNTER
最大频率@ Nom-Sup:3000000 Hz工作模式:SYNCHRONOUS
位数:5功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC20,.4SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED电源:3/15 V
传播延迟(tpd):400 ns认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Counters
最大供电电压 (Vsup):15 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:8.965 mm最小 fmax:3 MHz
Base Number Matches:1

HCF4018BC1 数据手册

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HCC/HCF4018B  
PRESETTABLE DIVIDE-BY-N COUNTER  
.
MEDIUM SPEED OPERATION - 10MHz (typ.)  
AT VDD – VSS = 10V  
FULLY STATIC OPERATION  
QUIESCENT CURRENT SPECIFIED TO 20V  
FOR HCC DEVICE  
STANDARDIZED SYMMETRICAL OUTPUT  
CHARACTERISTICS  
INPUT CURRENT OF 100nA AT 18V AND 25°C  
FOR HCC DEVICE  
100% TESTED FOR QUIESCENT CURRENT  
5V, 10V, AND 15V PARAMETRIC RATINGS  
MEETS ALLREQUIREMENTS OF JEDECTEN-  
TATIVE STANDARD No 13A, ”STANDARD  
SPECIFICATIONS FOR DESCRIPTION OF ”B”  
SERIES CMOS DEVICES”  
.
.
.
.
F
EY  
(Plastic Package)  
(Ceramic Frit Seal Package)  
.
.
.
C1  
M1  
(Plastic Chip Carrier)  
(Micro Package)  
ORDER CODES :  
HCC4018BF  
HCF4018BEY  
HCF4018BM1  
HCF4018BC1  
DESCRIPTION  
PIN CONNECTIONS  
The HCC4018B (extended temperature range) and  
HCF4018B (intermediate temperature range) are  
monolithic integrated circuit, available in 16-lead  
dual in-line plastic or ceramic package and plastic  
micropackage.  
The HCC/HCF4018B types consist of 5 Johnson-  
Counter stages, buffered Q outputs from each  
stage, and counter preset control gating. CLOCK,  
RESET, DATA, PRESET ENABLE, and 5 individual  
JAM inputs are provided. Divide by 10, 8, 6, 4, or 2  
counter configurations can be implemented byfeed-  
ing the Q5, Q4, Q3, Q2, Q1 signals, respectively,  
back to the DATA input.  
Divide-by-9, 7, 5, or 3 counter configurations can be  
implemented by the use of a HCC/HCF4011B gate  
package to properly gate the feedback connection  
to the DATA input. Divide-by-functions greater than  
10 can be achieved by use of multiple HCC/HCF  
4018B units. The counter is advanced one count at  
the positive clock-signal transition. Schmitt Trigger  
action on the clock line permits unlimited clock rise  
and fall times. A high RESET signal clears the  
counter to an all-zero condition. A high PRESENT-  
ENABLE signal allows information on the JAM in-  
puts to preset the counter. Anti-lock gating is  
provided to assure the proper counting sequence.  
June 1989  
1/12  

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