GS9000CCTJ

更新时间： 2024-01-14 16:07:51

品牌	Logo	应用领域
GENNUM		解码器
页数	文件大小	规格书
8页	110K
描述
Serial Digital Decoder

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中文翻译

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技术参数
数据手册

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GS9000CCTJ 技术参数

生命周期：	Obsolete	零件包装代码：	QLCC
包装说明：	,	针数：	28
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.84	Is Samacsys：	N
商用集成电路类型：	CONSUMER CIRCUIT	JESD-30 代码：	S-PQCC-J28
功能数量：	1	端子数量：	28
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装形状：	SQUARE
封装形式：	CHIP CARRIER	认证状态：	Not Qualified
最大供电电压 (Vsup)：	5.25 V	最小供电电压 (Vsup)：	4.75 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	J BEND
端子位置：	QUAD	Base Number Matches：	1

GS9000CCTJ 数据手册

EXT

SWC

6k8

OUTPUT

EXT

EXTERNAL

COMPONENTS

GND

Fig. 5 Pin 15 SWC

Fig. 6 Pins 3, 16, 17, 19 - 25, 27, 28

SWF, HSYNC, SSI, SSD, PCLK, PD0-9

t_CLKLt_CLKH

PARALLEL

DATA

(PDn)

50%

SERIAL

CLOCK

(SCI)

PARALLEL

CLOCK

(PCLK)

SERIAL

DATA

(SDI)

50%

t_HOLD

t_SU

t_D

Fig. 7 Waveforms

TEST SET-UP & APPLICATION INFORMATION

In order to maintain very short interconnections when

interfacing with the GS9005A Receiver, the critical high

speed inputs such as Serial Data (pins 5 and 6) and Serial

Clock (pins 7 and 8) are located along one side of the device

package.

Figure 8 shows the test set-up for the GS9000C operating

from a V_DDsupply of +5 volts. The differential pseudo ECL

inputs for DATA and CLOCK (pins 5,6,7 and 8) must be

biased between +3.0 and +4.0 volts. In the circuit shown,

these inputs with the resistor values shown, can be directly

drivenfromtheoutputsoftheGS9005AReclockingReceiver.

If the automatic standard select function is not used, the

Standard Select bits (pins 9 and 10) do not need to be

connected, however the control input (pin 11) should be

grounded.

In other cases, such as true ECL level driver outputs, two

biasing resistors are needed on the DATA and CLOCK inputs

and the signals must be AC coupled.

It is critical that the decoupling capacitors connected to pins

12,13 and 18 be chip types and be located as close as

possible to the device pins.

522 - 49 - 01

1 2 3 456 7 8

中文翻译

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