Datasheet > GS9000B

GS9000B

更新时间： 2024-02-17 14:56:37

品牌	Logo	应用领域
其他 - ETC		解码器
页数	文件大小	规格书
8页	148K
描述
GENLINX Serial Digital Decoder

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技术参数
数据手册

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GS9000B 技术参数

生命周期：	Obsolete	零件包装代码：	QLCC
包装说明：	,	针数：	28
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.84	Is Samacsys：	N
商用集成电路类型：	CONSUMER CIRCUIT	JESD-30 代码：	S-PQCC-J28
功能数量：	1	端子数量：	28
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装形状：	SQUARE
封装形式：	CHIP CARRIER	认证状态：	Not Qualified
最大供电电压 (Vsup)：	5.25 V	最小供电电压 (Vsup)：	4.75 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	J BEND
端子位置：	QUAD	Base Number Matches：	1

GS9000B 数据手册

GS9000B PIN DESCRIPTIONS

PIN NO.

SYMBOL

SWC

TYPE

DESCRIPTION

Input

Sync Warning Control. Analog input used to set the HSYNC Error Rate (HER). This is

accomplished by an external RC time constant connected to this pin.

PCLK

PD0

Output

Parallel Clock Output. CMOS (TTL compatible) clock output where the rising edge of the clock is

located at the centre of the parallel data window within a given tolerance. See Fig. 2.

Parallel Data Output - Bit 0 (LSB). CMOS (TTL compatible) descrambled parallel data output from the

serial to parallel convertor representing the least significant bit (LSB).

Power Supply. Most positive power supply connection.

19 - 25

PD1 - PD7

Outputs

Parallel Data Outputs - Bit 1 to Bit 7. CMOS (TTL compatible) descrambled parallel data outputs from

the serial to parallel convertor representing data bit 1 through data bit 7.

Power Supply. Most negative power supply connection.

PD8

Output

Parallel Data Output. CMOS (TTL compatible) descrambled parallel data output from the serial to

parallel convertor representing data bit 8.

PD9

Parallel Data Output - Bit 9 (MSB). CMOS (TTL compatible) descrambled data output from the serial

to parallel convertor representing the most significant bit (MSB).

INPUT / OUTPUT CIRCUITS

SDI

SCI

EXT

SSC

BIAS

SCE

EXTERNAL

COMPONENTS

SDI

SCI

Fig. 2 Pin 11 SSC

Fig. 3 Pin 14 SCE

Fig. 4 Pins 5 - 8 SDI - SCI

EXT

SWC

6800

OUTPUT

EXT

EXTERNAL

COMPONENTS

GND

Fig. 5 Pin 15 SWC

Fig. 6 Pins 3, 16, 17, 19 - 25, 27, 28

SWF, HSYNC, SSI, SSD, PCLK, PD0-9

521 - 79 - 01

1 2 345 6 7 8

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